EP2AGX260 datasheet(46/380 Pages) ALTERA

Part #	EP2AGX260

Description	Device Interfaces and Integration

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Manufacturer	ALTERA [Altera Corporation]

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46 / 380 page

2–16

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices

Adaptive Logic Modules

Arria II Device Handbook Volume 1: Device Interfaces and Integration

December 2010

Altera Corporation

Register Chain

In addition to general routing outputs, the ALMs in any given LAB have register

chain outputs to allow registers in the same LAB to be cascaded together. The register

chain interconnect allows a LAB to use LUTs for a single combinational function and

the registers to be used for an unrelated shift register implementation. These resources

speed up connections between ALMs while saving local interconnect resources (refer

to Figure 2–14). The Quartus II Compiler automatically takes advantage of these

resources to improve utilization and performance.

1 For more information about register chain interconnect, refer to “ALM Interconnects”

on page 2–17.

Figure 2–14. Register Chain in an LAB (Note 1)

Note to Figure 2–14:

(1) You can use the combinational or adder logic to implement an unrelated, un-registered function.

DQ

To general or

local routing

reg0

To general or

local routing

reg_chain_in

adder0

DQ

To general or

local routing

reg1

To general or

local routing

adder1

DQ

To general or

local routing

reg0

To general or

local routing

reg_chain_out

adder0

DQ

To general or

local routing

reg1

To general or

local routing

adder1

From previous ALM

in the LAB

To next ALM

in the LAB

Combinational

Logic

Combinational

Logic

labclk

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