 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
EP2AGZ350 Datasheet(PDF) 56 Page - Altera Corporation |
|
||||||||||||||||||||||||||||||
EP2AGZ350 Datasheet(HTML) 56 Page - Altera Corporation |
|
|
56 / 380 page  3–8 Chapter 3: Memory Blocks in Arria II Devices Memory Features Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2011 Altera Corporation Mixed Width Support M9K and M144K blocks support mixed data widths inherently. MLABs can support mixed data widths through emulation with the Quartus II software. When using simple dual-port, true dual-port, or FIFO modes, mixed width support allows you to read and write different data widths to a memory block. For more information about the different widths supported per memory mode, refer to “Memory Modes” on page 3–10. 1 MLABs do not support mixed-width FIFO mode. Asynchronous Clear Arria II memory blocks support asynchronous clears on the output latches and output registers. Therefore, if your RAM is not using output registers, you can still clear the RAM outputs using the output latch asynchronous clear. Figure 3–7 shows a functional waveform showing this functionality. You can selectively enable asynchronous clears per logical memory using the RAM MegaWizard Plug-In Manager. f For more information about the RAM MegaWizard Plug-In Manager, refer to the Internal Memory (RAM and ROM) Megafunction User Guide. Error Correction Code Support Arria II GZ M144K blocks have built-in support for ECC when in ×64-wide simple dual-port mode. ECC allows you to detect and correct data errors in the memory array. The M144K blocks have a single-error-correction double-error-detection (SECDED) implementation. SECDED can detect and fix a single bit error in a 64-bit word, or detect two bit errors in a 64-bit word. It cannot detect three or more errors. The M144K ECC status is communicated using a three-bit status flag (eccstatus[2..0]). The status flag can be either registered or unregistered. When registered, it uses the same clock and asynchronous clear signals as the output registers. When unregistered, it cannot be asynchronously cleared. Figure 3–7. Output Latch Asynchronous Clear Waveform aclr aclr at latch q outclk |
Similar Part No. - EP2AGZ350 |
|
Similar Description - EP2AGZ350 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
