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NCP5378 Datasheet(PDF) 5 Page - ON Semiconductor |
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NCP5378 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 18 page NCP5378 http://onsemi.com 5 ELECTRICAL CHARACTERISTICS 0°C < TA < 70°C; 0°C < TJ < 125°C; 4.75 < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF unless otherwise noted. Parameter Test Conditions Min Typ Max Unit ERROR AMPLIFIER Input Bias Current −200 − 200 nA Open Loop DC Gain CL = 60 pF to GND, RL = 10 kW to GND − 100 − dB Open Loop Unity Gain Bandwidth CL = 60 pF to GND, RL = 10 kW to GND − 18 − MHz Open Loop Phase Margin CL = 60 pF to GND, RL = 10 kW to GND − 70 − ° Slew Rate DVin = 100 mV, G = −10V/V, DVout = 1.5 V − 2.5 V, CL = 60 pF to GND, DC Load = ±125 mA to GND − 10 − V/ms Maximum Output Voltage 10 mV of Overdrive, ISOURCE = 2.0 mA 3.0 − − V Minimum Output Voltage 10 mV of Overdrive, ISINK = 500 mA − − 75 mV Output Source Current 10 mV of Overdrive, Vout = 3.5 V 1.5 2.0 − mA Output Sink Current 10 mV of Overdrive, Vout = 0.1 V 0.65 1.0 − mA DIFFERENTIAL SUMMING AMPLIFIER V+ Input Pull down Resistance DRVON = low DRVON = high − − 0.6 6.0 − − kW V+ Input Bias Voltage DRVON = low DRVON = high − 0.8 0.05 0.88 0.1 0.95 V Input Voltage Range (Note 3) −0.3 − 3.0 V −3 dB Bandwidth CL = 80 pF to GND, RL = 10 kW to GND − 15 − MHz Closed Loop DC gain VS to Diffout (Note 3) VS+ to VS− = 0.5 V to 1.6 V 0.98 1.0 1.02 V/V Maximum Output Voltage 10 mV of Overdrive, ISOURCE = 2 mA 3.0 − − V Minimum Output Voltage 10 mV of Overdrive, ISINK = 1 mA − − 0.5 V Output Source Current 10 mV of Overdrive, Vout = 3 V 1.5 2.0 − mA Output Sink Current 10 mV of Overdrive, Vout = 0.2 V 1.0 1.5 − mA INTERNAL OFFSET VOLTAGE Offset Voltage to the (+) Pin of the Error Amp & the VDRP Pin −2 0 +2 mV VDROOP AMPLIFIER Input Bias Current −200 − 200 nA Inverting Voltage Range 0 1.3 3.0 V Open Loop DC Gain CL = 20 pF to GND including ESD RL = 1 kW to GND − 100 − dB Open Loop Unity Gain Bandwidth CL = 20 pF to GND including ESD RL = 1 kW to GND − 18 − MHz 3. Guaranteed by design. 4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram. |
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