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PD488588FF Datasheet(PDF) 32 Page - Elpida Memory |
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PD488588FF Datasheet(HTML) 32 Page - Elpida Memory |
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32 / 79 page  Data Sheet E0251N20 (Ver. 2.0) 32 µµµµPD488588FF-C80-40 19. Control Register Transactions The RDRAM has two CMOS input pins SCK and CMD and two CMOS input/output pins SIO0 and SIO1. These provide serial access to a set of control registers in the RDRAM. These control registers provide configuration information to the controller during the initialization process. They also allow an application to select the appropriate operating mode of the RDRAM. SCK (serial clock) and CMD (command) are driven by the controller to all RDRAMs in parallel. SIO0 and SIO1 are connected (in a daisy chain fashion) from one RDRAM to the next. In normal operation, the data on SIO0 is repeated on SIO1, which connects to SIO0 of the next RDRAM (the data is repeated from SIO1 to SIO0 for a read data packet). The controller connects to SIO0 of the first RDRAM. Write and read transactions are each composed of four packets, as shown in Figure 19-1 and Figure 19-2. Each packet consists of 16 bits, as summarized in Table 20-1 and Table 20-2. The packet bits are sampled on the falling edge of SCK. A transaction begins with a SRQ (Serial Request) packet. This packet is framed with a 11110000 pattern on the CMD input (note that the CMD bits are sampled on both the falling edge and the rising edge of SCK). The SRQ packet contains the SOP3..SOP0 (Serial Opcode) field, which selects the transaction type. The SDEV5..SDEV0 (Serial Device address) selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is set, then all RDRAMs are selected. The SA (Serial Address) packet contains a 12 bit address for selecting a control register. A write transaction has a SD (Serial Data) packet next. This contains 16 bits of data that is written into the selected control register. A SINT (Serial Interval) packet is last, providing some delay for any side-effects to take place. A read transaction has a SINT packet, then a SD packet. This provides delay for the selected RDRAM to access the control register. The SD read data packet travels in the opposite direction (towards the controller) from the other packet types. The SCK cycle time will accommodate the total delay. Figure 19-1 Serial Write (SWR) Transaction to Control Register SRQ - SWR command 1111 00000000...00000000 SRQ - SWR command 0000 SA SA SD SD SINT SINT 00000000...00000000 00000000...00000000 00000000...00000000 SCK CMD SIO0 SIO1 T4 T36 T20 T52 T68 Each packet is repeated from SIO0 to SIO1 1 1 1 1 0 0 0 0 1111 next transaction Figure 19-2 Serial Read (SRD) Transaction Control Register SRQ - SRD command 1111 00000000...00000000 SRQ - SRD command 0000 SA SA SINT SINT SD SD 00000000...00000000 00000000...00000000 00000000...00000000 SCK CMD SIO 0 SIO 1 T4 T36 T20 T52 T68 First 3 packets are repeated from SIO0 to SIO1 1 1 1 1 0 0 0 0 1111 next transaction 0 0 addressed RDRAM devices 0/SD15..SD0/0 on SIO0 controller drives 0 on SIO0 non addressed RDRAMs pass 0/SD15..SD0/0 from SIO1 to SIO0 0 0 |
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