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ADS5542IPAPRG4 Datasheet(PDF) 7 Page - Texas Instruments |
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ADS5542IPAPRG4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 33 page www.ti.com RESET TIMING CHARACTERISTICS RESET (Pin 35) t1 . 10 ms t2 . 2 ms t3 . 2 ms SEN Active Power Supply (AVDD, DRVDD) SERIAL PROGRAMMING INTERFACE CHARACTERISTICS A3 ADDRESS SDATA MSB DATA A2 A1 A0 D11 D10 D9 D0 ADS5542 SBAS308D – MAY 2004 – REVISED FEBRUARY 2007 Typical values given at T A = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRV DD = 3.3 V, and 3-VPP differential clock, unless otherwise noted PARAMETER DESCRIPTION MIN TYP MAX UNIT Switching Specification t1 Power-on delay Delay from power-on of AVDD and DRVDD to RESET pulse 10 ms active t2 Reset pulse width Pulse width of active RESET signal 2 µs t3 Register write delay Delay from RESET disable to SEN active 2 µs Power-up time Delay from power-up of AVDD and DRVDD to output stable 40 ms Figure 2. Reset Timing Diagram The ADS5542 has a three-wire serial interface. The ADS5542 latches serial data SDATA on the falling edge of serial clock SCLK when SEN is active. • Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge. • Minimum width of data stream for a valid loading is 16 clocks. • Data is loaded at every 16th SCLK falling edge while SEN is low. • In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. • Data can be loaded in multiples of 16-bit words within a single active SEN pulse. • The first 4-bit nibble is the address of the register while the last 12 bits are the register contents. Figure 3. DATA Communication is 2-Byte, MSB First 7 Submit Documentation Feedback |
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