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PE42720 Datasheet(PDF) 8 Page - Peregrine Semiconductor |
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PE42720 Datasheet(HTML) 8 Page - Peregrine Semiconductor |
8 / 11 page Product Specification PE42720 Page 8 of 11 Document No. DOC-12514-2 │ UltraCMOS® RFIC Solutions ©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Figure 19. Evaluation Board Layout Evaluation Kit The SPDT switch evaluation board was designed to ease customer evaluation of Peregrine’s PE42720. The RF common port is connected through a 75Ω transmission line via the F-Type connector, J2. RF1 and RF2 ports are connected through 75Ω transmission lines via F-Type connectors J1 and J3, respectively. A 75Ω through transmission line is available via F-Type connectors J4 and J5, which can be used to de-embed the loss of the PCB. J6 provides DC and digital inputs to the device. The board is constructed of a four metal layer material with a total thickness of 60 mils. To achieve high isolation, the 75Ω transmission lines are designed in layer 2 using a stripline waveguide design. The board stack up for 75Ω transmission lines has 20 mil thickness of Rogers 4350B between layer 1 and layer 2, 20 mil thickness of Rogers 4450F between layer 2 and layer 3, and 13.3 mil thickness of Rogers 4350B between layer 3 and layer 4. For the true performance of the PE42720 to be realized, the PCB should be designed in such a way that RF transmission lines and sensitive DC I/O traces are heavily isolated from one another. 101-0557 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com |
Similar Part No. - PE42720_14 |
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Similar Description - PE42720_14 |
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