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PE43705 Datasheet(PDF) 9 Page - Peregrine Semiconductor |
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PE43705 Datasheet(HTML) 9 Page - Peregrine Semiconductor |
9 / 18 page PE43705 Product Specification ©2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-47804-2 | www.psemi.com Page 9 of 18 VDD = 3.4V or 5.0V, -40°C < TA < 105°C, unless otherwise specified VDD = 3.4V or 5.0V, -40°C < TA < 105°C, unless otherwise specified Figure 4. Serial Timing Diagram Figure 5. Latched Parallel/Direct Parallel Timing Diagram Parameter Symbol Min Max Unit Serial clock frequency FCLK 10 MHz Serial clock HIGH time TCLKH 30 ns Serial clock LOW time TCLKL 30 ns Last serial clock rising edge setup time to Latch Enable rising edge TLESU 10 ns Latch enable min. pulse width TLEPW 30 ns Serial data setup time TSISU 10 ns Serial data hold time TSIH 10 ns Parallel data setup time TDISU 100 ns Parallel data hold time TDIH 100 ns Address setup time TASU 100 ns Address hold time TAH 100 ns Parallel/serial setup time TPSSU 100 ns Parallel/serial hold time TPSH 100 ns Digital register delay (internal) TPD 10 ns Parameter Symbol Min Max Unit Latch enable minimum pulse width TLEPW 30 ns Parallel data setup time TDISU 100 ns Parallel data hold time TDIH 100 ns Parallel/serial setup time TPSSU 100 ns Parallel/serial hold time TPSIH 100 ns Digital register delay (internal) TPD 10 ns Digital register delay (internal, direct mode only) TDIPD 5 ns VALID T DISU T DIH DI[6:0] LE P/S T PSSU T PSH T LEPW VALID DO[6:0] T DIPD T PD Table 13. Parallel and Direct Interface AC Characteristics Table 12. Serial Interface AC Characteristics D[7] must be set to logic low Bits can either be set to logic high or logic low D[0] D[1] D[2] D[3] D[4] D[5] D[7] T SISU T CLKL T LEPW T SIH T CLKH SI CLK LE P/S T LESU T PSSU T PSIH VALID T DISU T PD T DIH D[6] DI[6:0] DO[6:0] Table 11. Latch and Clock Specifications Latch Enable Function 0 Shift register clocked ↑ Contents of shift register transferred to attenuator core Shift Clock ↑ X |
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