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M2S005 Datasheet(PDF) 7 Page - Microsemi Corporation |
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M2S005 Datasheet(HTML) 7 Page - Microsemi Corporation |
7 / 27 page 7 www.microsemi.com/products/fpga-soc/fpga/igloo-e • Ultra low power FPGAs • Flash*Freeze technology for lowest power consumption • 1.2 V core and I/O voltage • Instant-on • AES-protected in-system programming (ISP) • User nonvolatile FlashROM IGLOO/e Notes: 1. AES is not available for Cortex-M1 IGLOO devices. 2. AGL060 in CS121 does not support the PLL. 3. Six chip (main) and twelve quadrant global networks are available for AGL060 devices and above. 4. The M1AGL250 device does not support this package. 5. Device/package support TBD. IGLOO/e Devices Notes: 1. The M1AGL250 device does not support QN132 or CS196 packages. 2. Each used differential pair reduces the number of single-ended I/Os available by two. 3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one. 4. Device/package support TBD. 5. FG256 and FG484 are footprint-compatible packages. I/Os Per Package IGLOO Devices AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 AGLE600 AGLE3000 ARM-Enabled IGLOO Devices M1AGL250 M1AGL600 M1AGL1000 M1AGLE3000 I/O Package Single- Ended I/O Single- Ended I/O Single- Ended I/O Single- Ended I/O2 Differen- tial I/O Pairs Single- Ended I/O2 Differen- tial I/O Pairs Single- Ended I/O2 Differen- tial I/O Pairs Single- Ended I/O2 Differen- tial I/O Pairs Single- Ended I/O2 Differen- tial I/O Pairs Single- Ended I/O2 Differen- tial I/O Pairs QN48 34 — — — — — — — — — — — — — — QN68 49 — — — — — — — — — — — — — — UC81 66 — — — — — — — — — — — — — — CS81 66 — — 60 7 — — — — — — — — — — CS121 — 96 96 — — — — — — — — — — — — VQ100 77 71 71 68 13 — — — — — — — — — — QN132 81 80 84 871,4 191,4 — — — — — — — — — — CS196 — — 133 1431 351 143 35 — — — — — — — — FG144 — 967 97 97 24 97 25 97 25 97 25 — — — — FG2565 — — — — — 178 38 177 43 177 44 165 79 — — CS281 — — — — — — — 215 53 215 53 — — — — FG4845 — — — — — 194 38 235 60 300 74 270 135 341 168 FG896 — — — — — — — — — — — — — 620 310 The ultra low power programmable solution The IGLOO family of reprogrammable, full-featured flash FPGAs is designed to meet the demanding power, area and cost requirements of today’s portable electronics. Based on nonvolatile flash technology, the 1.2 V to 1.5 V operating voltage family offers the industry’s lowest power consumption—as low as 5 µW. The IGLOO family supports up to 3,000,000 system gates with up to 504 Kbits of true dual-port SRAM, up to 6 embedded PLLs and up to 620 user I/Os. Low power applications that require 32-bit processing can use the ARM Cortex-M1 processor without license fee or royalties in M1 IGLOO devices. Developed specifically for implementation in FPGAs, Cortex-M1 devices offer an optimal balance between performance and size to minimize power consumption. IGLOO Devices AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 AGLE600 AGLE3000 ARM-Enabled IGLOO Devices2 M1AGL250 M1AGL600 M1AGL1000 M1AGLE3000 System Gates 30,000 60,000 125,000 250,000 400,000 600,000 1,000,000 600,000 3,000,000 Typical Equivalent Macrocells 256 512 1,024 2,048 — — — — — VersaTiles (D-flip-flops) 768 1,536 3,072 6,144 9,216 13,824 24,576 13,824 75,264 Flash*Freeze Mode (typical, µW) 5 10 16 24 32 36 53 49 137 RAM (1,024 bits) — 18 36 36 54 108 144 108 504 RAM Blocks (4,608 bits) — 4 8 8 12 24 32 24 112 FlashROM Kbits (1,024 bits) 1 1 1 1 1 1 1 1 1 AES-Protected ISP1 — Yes Yes Yes Yes Yes Yes Yes Yes Integrated PLLs with CCC2 — 1 1 1 1 1 1 6 6 VersaNet Globals3 6 18 18 18 18 18 18 18 18 I/O Banks 2 2 2 4 4 4 4 8 8 Maximum User I/Os 81 96 133 143 194 235 300 270 620 Package Pins UC CS QN VQ FG UC81 CS81 QN48 QN68 QN132 VQ100 CS1213 QN132 VQ100 FG1446 CS196 QN132 VQ100 FG144 CS81 CS1964 QN1324,5 VQ100 FG144 CS196 FG144 FG256 FG484 CS281 FG144 FG256 FG484 CS281 FG144 FG256 FG484 FG256 FG484 FG484 FG896 |
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