AD9644BCPZRL7-80 datasheet(1/44 Pages) AD

Part #	AD9644BCPZRL7-80

Description	14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual Serial Output Analog-to-Digital Converter (ADC)

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14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual

Serial Output Analog-to-Digital Converter (ADC)

Data Sheet

AD9644

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

JESD204A coded serial digital outputs

SNR = 73.7 dBFS at 70 MHz and 80 MSPS

SNR = 71.7 dBFS at 70 MHz and 155 MSPS

SFDR = 92 dBc at 70 MHz and 80 MSPS

SFDR = 92 dBc at 70 MHz and 155 MSPS

Low power: 423 mW at 80 MSPS, 567 mW at 155 MSPS

1.8 V supply operation

Integer 1-to-8 input clock divider

IF sampling frequencies to 250 MHz

−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS

−150.3 dBFS/Hz input noise at 180 MHz and 155 MSPS

Programmable internal ADC voltage reference

Flexible analog input range: 1.4 V p-p to 2.1 V p-p

ADC clock duty cycle stabilizer

Serial port control

User-configurable, built-in self-test (BIST) capability

Energy-saving power-down modes

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers (3G and 4G)

GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Broadband data applications

Ultrasound equipment

FUNCTIONAL BLOCK DIAGRAM

REFERENCE

AD9644

14

VIN+A

AVDD

PDWN

DRVDD

DRGND

14

VIN+B

VIN–B

DOUT+A

DOUT+B

VIN–A

VCMA

VCMB

SCLK SDIO CSB

PIPELINE

14-BIT ADC

PIPELINE

14-BIT ADC

SERIAL PORT

(SPI)

CLK+ CLK–

1 TO 8

CLOCK

DIVIDER

DSYNC+A

PLL

DSYNC+B

AGND

SYNC

DOUT–A

DSYNC–A

DOUT–B

DSYNC–B

Figure 1. 48-Lead 7 mm × 7 mm LFCSP

PRODUCT HIGHLIGHTS

1.

An on-chip PLL allows users to provide a single ADC

sampling clock; the PLL multiplies the ADC sampling

clock to produce the corresponding JESD204A data rate

clock.

2.

The configurable JESD204A output block supports up to

1.6 Gbps per channel data rate when using a dedicated

data link per ADC or 3.2 Gbps data rate when using a

single shared data link for both ADCs.

3.

Proprietary differential input that maintains excellent SNR

performance for input frequencies up to 250 MHz.

4.

Operation from a single 1.8 V power supply.

5.

Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary, twos complement, or gray coding),

controlling the clock DCS, power-down, test modes,

voltage reference mode, and serial output configuration.

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