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ACT8897Q4I1PQ-T Datasheet(PDF) 5 Page - Active-Semi, Inc |
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ACT8897Q4I1PQ-T Datasheet(HTML) 5 Page - Active-Semi, Inc |
5 / 32 page ACT8897 Rev 2, 05-Sep-13 - 5 - www.active-semi.com ActivePMU TM is trademark of Active-Semi. I2CTM is a trademark of NXP. Copyright © 2013 Active-Semi, Inc. Innovative PowerTM Active-Semi Proprietary―For Authorized Recipients and Customers PIN DESCRIPTIONS PIN NAME DESCRIPTION 1 OUT1 Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. 2 GA Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1,GP2 and GP3 together at a single point as close to the IC as possible. 3 OUT4 Output Voltage for REG4. Capable of delivering up to 150mA of output current. Connect a 1.5µF ceramic capacitor from OUT4 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled. 4 OUT5 Output Voltage for REG5. Capable of delivering up to 150mA of output current. Connect a 1.5µF ceramic capacitor from OUT5 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled. 5 INL45 Power Input for REG4 and REG5. Bypass to GA with a high quality ceramic capacitor placed as close to the IC as possible. 6 INL67 Power Input for REG6 and REG7. Bypass to GA with a high quality ceramic capacitor placed as close to the IC as possible. 7 OUT6 Output Voltage for REG6. Capable of delivering up to 250mA of output current. Connect a 2.2µF ceramic capacitor from OUT6 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled. 8 OUT7 Output Voltage for REG7. Capable of delivering up to 250mA of output current. Connect a 2.2µF ceramic capacitor from OUT7 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled. 9 nPBIN Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor to enable the IC, drive nPBIN directly to GA to assert a manual reset condition. Refer to the nPBIN Multi-Function Input section for more information. nPBIN is internally pulled up to VVDDREF through a 35kΩ resistor. 10 PWRHLD Power Hold Input. Refer to the Control Sequences section for more information. 11 nRSTO Active Low Reset Output. See the nRSTO Output section for more information. 12 nIRQ Open-Drain Interrupt Output. nIRQ asserts any time an unmasked fault condition exists or an interrupt occurs. See the nIRQ Output section for more information. 13 nPBSTAT Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the nPBIN is pushed, and is high-Z otherwise. See the nPBSTAT Output section for more information. 14 GP3 Power Ground for REG3. Connect GA, GP1, GP2, and GP3 together at a single point as close to the IC as possible. 15 SW3 Switching Node Output for REG3. Connect this pin to the switching end of the inductor. 16 VP3 Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close to the IC as possible. 17 PWREN Power Enable Input. Refer to the Control Sequences section for more information. 18 NC1 Connect NC1 to GA. 19 OUT3 Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. 20 VSEL Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage. Drive to logic high to select secondary output voltage. See the Output Voltage Programming section for more information. 21 SCL Clock Input for I2C Serial Interface. 22 SDA Data Input for I2C Serial Interface. Data is read on the rising edge of SCL. |
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