Triple Output Step-Down Switching Regulator

A4490

7

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Basic Operation

The A4490 contains three fixed frequency, buck switching con-

verters with peak current-mode control, including slope compen-

sation. Each converter can be independently turned on and off via

the enable inputs (EN1, EN2, and EN3), which are active high.

When enabled, the corresponding output is brought-up under the

control of a soft start routine, which avoids output voltage over-

shoot and minimizes input inrush current.

The output voltage is typically divided down by an external

potential divider, and is compared against an internal reference

voltage to produce an error signal, also known as the current

demand signal. The current signal through the buck switch is

converted into a voltage. This signal is then compared against the

current demand signal to create the required duty cycle.

At the beginning of each switching cycle, the buck switch is

turned on. When the current signal through the switch reaches the

level of the current demand signal, the on-time of the switch is

terminated. On the next switching cycle, the switch is turned on

again and the cycle is repeated.

One shared clock is used to define the switching frequency for

each regulator. Each of the three switching cycles (REG1, REG2,

and REG3) are phase shifted with respect to one another by 120°

in an attempt to minimize the pulsed current drawn from the

input filter capacitors. Under certain conditions, for example at

switching overlap between channels is inevitable.

cause duty cycles (DC) of less than the minimum value, the

converter enters a pulse-skipping mode to ensure regulation is

maintained.

A charge pump regulator is provided to ensure a sufficient gate

drive is available for all three power switches across the full input

voltage range. This regulator allows operation even at very wide

operating duty cycles. On initial power-up, an internal regulator

is used to provide the bias supply for on-chip control functions.

Each regulator channel utilizes pulse-by-pulse current limiting in

the event of either a short circuit or an overload. If the overload

is applied long enough, the IC temperature may rise sufficiently

to cause the thermal shutdown circuit to operate. The part will

auto-restart under control of the soft start circuit after the thermal

disable condition is removed, and assuming all other conditions

are met. See the Shutdown section for more information.

Power Configuration

The A4490 supports alternative schemes for providing logic sup-

ply voltage on the VDD pin. In addition, the IC can be powered

up and down using either the VBB or ENB pins.

Powering VDD To minimize power dissipation, especially at

high input voltages, it is recommended that an external sup-

ply be applied to the VDD input pin. Typically, this voltage is

derived from one of the three regulated outputs that are set-up for

Another advantage of powering the VDD externally is that the

VBB undervoltage lockout level is lowered. To maximize the

run time of the switchers during a VBB power-down condition,

two alternative undervoltage shutdown conditions are supported,

depending on which VDD-powering configuration has been

implemented. When no external VDD is applied, the minimum

One note of caution when deriving VDD from a VREG output:

matically starts from the internal regulator because VREG has not

yet reached regulation. This means the startup threshold is deter-

VDD. When VREG has begun to supply VDD externally, the

Powering Up and Down with VBB Referring to figure 1,

each of the enable inputs (ENBx) are held high by being tied to

three regulator channels (VREGx). When all three regulators

have reached the 85% FBx threshold, the power-on-reset timer

specification.

Functional Description