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AK5720VT Datasheet(PDF) 11 Page - HuaXinAn Electronics CO.,LTD |
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AK5720VT Datasheet(HTML) 11 Page - HuaXinAn Electronics CO.,LTD |
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11 / 25 page  [AK5720] MS1641-J-00 2014/04 - 10 - Parameter Symbol min typ max Unit Audio Interface Timing (Slave mode) Normal mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “” (Note 8) BICK “” to LRCK Edge (Note 8) LRCK to SDTO (MSB) (Except I 2S mode) BICK “” to SDTO tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 160 65 65 30 30 35 35 ns ns ns ns ns ns ns TDM256 mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “” (Note 8) BICK “” to LRCK Edge (Note 8) SDTO Setup time BICK “” SDTO Hold BICK “” TDMI Hold Time TDMI Setup Time tBCK tBCKL tBCKH tLRB tBLR tBSS tBSH tSDH tSDS 40 16 16 10 10 7 6 4 5 ns ns ns ns ns ns ns ns ns Audio Interface Timing (Master mode) Normal mode BICK Frequency BICK Duty BICK “” to LRCK BICK “” to SDTO fBCK dBCK tMBLR tBSD 20 40 64fs 50 20 40 Hz % ns ns TDM256 mode BICK Frequency BICK Duty (Note 9) BICK “” to LRCK SDTO Setup time BICK “” SDTO Hold BICK “” TDMI Hold Time TDMI Setup Time fBCK dBCK tMBLR tBSS tBSH tSDH tSDS 10 7 6 4 5 256fs 50 10 Hz % ns ns ns ns ns Power-Down & Reset Timing PDN Pulse Width (Note 10) PDN Reject Pulse Width (Note 10) PDN “” to SDTO valid (Note 11) tPD tRPD tPDV 150 4129 30 ns ns 1/fs Note 8. この規格値はLRCKのエッジとBICKの“”が重ならないように規定しています。 Note 9. MCLKのデューティが50%のとき。 Note 10. 電源投入時はPDN pin を“L” にすることでリセットがかかります。150ns以上のPDN pin = “L”パ ルスでリセットがかかります。30ns以下のPDN pin= “L”パルスではリセットはかかりません。 Note 11. PDN pin を立ち上げてからのLRCKクロックの “” の回数です。 |
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