AK8160BV datasheet(11/16 Pages) HUAXINAN

Part #	AK8160BV

Description	Low Power & Low Jitter Clock Generator for PCI Express

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Manufacturer	HUAXINAN [HuaXinAn Electronics CO.,LTD]

Direct Link	http://www.huaandz.com

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11 / 16 page

[AK8160BV]

Draft-E-00

2014/03

- 11 -

Tslew_delta (%) = 100 * 2 * (Tr - Tf) / (Tr + Tf)

Figure 7. Definition of Time Matching of Output Rising and Falling

Toutdc (%) = 100 * Thigh / Tperiod

Figure 8. Definition of Output Duty Cycle

Figure 9. Definition of Output Ring Back Voltage Margin

PCIE0/1p

PCIE0/1n

Vcross_median

+75mV

Vcross_median

-75mV

Tf

Tr

Vcross_median

Ring Back

Differential (PCIE0/1p)-(PCIE0/1n)

Ring Back

Vrb_max=100mV

Vrb_min=-100mV

Prohibited Ring Back Voltage Range

Thigh

0.0V

Tperiod

Differential (PCIE0/1p)-(PCIE0/1n)

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