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PE43204 Datasheet(PDF) 5 Page - Peregrine Semiconductor Corp.

Part # PE43204
Description  50 廓 RF Digital Attenuator
Download  8 Pages
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Manufacturer  PEREGRINE [Peregrine Semiconductor Corp.]
Direct Link  http://www.peregrine-semi.com
Logo PEREGRINE - Peregrine Semiconductor Corp.

PE43204 Datasheet(HTML) 5 Page - Peregrine Semiconductor Corp.

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Product Specification
PE43204
Page 5 of 8
Document No. 70-0257-03
│ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The 2-bit DSA EK Board was designed to ease
customer evaluation of Peregrine’s PE43204.
For automated programming, connect the test
harness provided with the EVK to the parallel port
of the PC and to the 6-pin header of the
PCB.
Connect the loose wire of the supplied
cable to a power supply set at 3.3V DC.
Set the
SP3T switches S1 and S2 to the ‘MIDDLE’ toggle
position.
After downloading and installing the
DSA EVK software from www.psemi.com, run the
software and select ‘PE43204’ from the drop down
menu. Using the software, enable or disable
each setting to the desired attenuation state. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
For manual programming, disconnect the test
harness provided with the EVK. Apply 3.3V to
the Vdd header pin and Ground to the GND
header pin. The DUT can be controlled two ways:
1. The mechanical switches in conjunction with
the VCTL pin can be used. Apply desired control
voltage to VCTL header pin. The top mechanical
switch controls the 6dB stage, the bottom
mechanical switch controls the 12dB stage. For
each switch, the left position is the 0V condition,
while the right position is the Vctrl condition. The
middle position leaves the control pin floating.
2. The CTL1 and CTL2 pins on the header can be
used. Each pin directly controls the 6dB and 12dB
stage respectively. The VCTL pin on the header is
left open. The mechanical switches may be left
uninstalled or must be kept in the middle position.
Note: To minimize switching time, C3 and C4 can
be removed.
Power-up Control Settings
The PE43204 will always power up into the state
determined by the voltages on the 2 control pins.
The DSA can be preset to any state within the 18
dB range by pre-setting the parallel control pins
prior to power-up. There is a 10
µs delay between
the time the DSA is powered-up to the time the
desired state is set. If the control pins are left
floating during power-up, the device will default to
the minimum attenuation setting (insertion loss
state).
Figure 14. Evaluation Board Layouts
Figure 15. Evaluation Board Schematic
Peregrine Specification 102/0416
Peregrine Specification 101/0344
Z=50 Ohm
De-embeding trace
Z=50 Ohm
Z=50 Ohm
CENTER GND PAD
3
1
2
4
S1
SS14MDP2
1
J2
SMASM
1
J5
SMASM
1
J4
SMASM
1
J3
SMASM
3
1
2
4
S2
SS14MDP2
1
1
3
3
5
5
2
2
4
4
6
6
J1
HEADER 3X2
RF2
RF2
RF1
RF1
NC
NC
1
2
8
9
7
3
13
U1
PE43204
C1
0.1µF
C2
100pF
C3
10PF
C4
10PF
VCTL
CTL2
VDD
CTL1


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