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THS7376 Datasheet(PDF) 8 Page - Texas Instruments |
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THS7376 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 62 page  THS7376 SBOS692 – JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS: VS+ = +5 V (continued) At TA = +25°C, RL = 150 Ω to GND, CLOAD = 5 pF, filter mode, and dc-coupled input and output, unless otherwise noted. See Figure 123 and Figure 124. TEST LEVEL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS (1) OUTPUT CHARACTERISTICS RL = 150 Ω to +2.5 V 4.85 V C RL = 150 Ω to GND 4.4 4.75 V A High output voltage swing RL = 75 Ω to +2.5 V 4.75 V C RL = 75 Ω to GND 4.5 V C RL = 150 Ω to +2.5 V (VIN = –0.2 V) 0.09 V C RL = 150 Ω to GND (VIN = –0.2 V) 0.05 0.1 V A Low output voltage swing RL = 75 Ω to +2.5 V (VIN = –0.2 V) 0.15 V C RL = 75 Ω to GND (VIN = –0.2 V) 0.05 V C Output current (sourcing) RL = 10 Ω to +2.5 V 150 mA C Output current (sinking) RL = 10 Ω to +2.5 V 140 mA C POWER SUPPLY Operating voltage 2.85 5 5.5 V B VIN = 0 V, enabled, VDISABLE = 0 V 27.2 32.6 39 mA A Total quiescent current, no load VIN = 0 V, disabled, VDISABLE = 3 V 0.1 10 µA A PSRR Power-supply rejection ratio At dc 53 dB C LOGIC CHARACTERISTICS(6) VIH High-level input voltage Disabled or HD bypass engaged 2.2 2.1 V A VIL Low-level input voltage Enabled or HD bypass disengaged 0.8 0.75 V A IIH High-level input current Applied voltage = 3 V 1 μA C IIL Low-level input current Applied voltage = 0 V 0.1 μA C tdis Disable time Disable pin transitions from low to high 100 ns C ten Enable time Disable pin transitions from high to low 200 ns C HD bypass and 10 ns C filter switch time (6) The logic input pins default to a logic '0' condition when left floating. Table 1. Logic Table DEFAULT LOGIC PIN NAME INPUT, OUTPUT LOGIC STATES DESCRIPTION STATE 0 0 All channels enabled Disable Input 0 1 All channels disabled 0 0 HD channels use 8th-order low-pass filters HD bypass Input 0 1 HD channels bypass low-pass filters 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: THS7376 |
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