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ADC16DV160 Datasheet(PDF) 11 Page - Texas Instruments |
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ADC16DV160 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 36 page  tSU Valid Data tH tPL tPH Valid Data 16 th clock SCLK SDIO Vin CLK+ CLK- OUTCLK+ OUTCLK- Dx+/- SampleN SampleN+12 Latency TP TP Tsu odd bits* even bits* Th Word N Word N-1 Word N+1 even bits* odd bits* even bits* * even bits: D0(LSB), D2, D4, D6, D8, D10, D12, D14 odd bits: D1, D3, D5, D7, D9, D11, D13, D15(MSB) odd bits* SampleN+11 ADC16DV160 www.ti.com SNAS488G – AUGUST 2009 – REVISED AUGUST 2011 Unless otherwise specified, the following specifications apply: VA3.0 = 3.0V, VA1.8 = 1.8V, VDR = 1.8V, Differential sinusoidal clock, fCLK = 160 MSPS at 2.8 VPP, AIN = -1dBFS, LVDS RTERM = 100Ω, CL = 5 pF. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C, unless otherwise noted. Symbol Parameter Conditions Typ Max Units MHz fSCLK Serial Clock Frequency fSCLK = 1 / tP 20 (max) 40 % (min) tPH SCLK Pulse Width - High % of SCLK Period 60 % (max) 40 % (min) tPL SCLK Pulse Width - Low % of SCLK Period 60 % (max) tSSU SDIO Input Data Setup Time 5 ns (min) tSH SDIO Input Data Hold Time 5 ns (min) tODZ SDIO Output Data Driven-to-Tri-State Time 5 ns (max) tOZD SDIO Output Data Tri-State-to-Driven Time 5 ns (max) tOD SDIO Output Data Delay Time 15 ns (max) tCSS CSB Setup Time 5 ns (min) tCSH CSB Hold Time 5 ns (min) Minimum time CSB must be tIAG Inter-access Gap 30 ns (min) deasserted between accesses Timing Diagrams Figure 3. Digital Output Timing Figure 4. SPI Write Timing Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADC16DV160 |
Similar Part No. - ADC16DV160_14 |
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Similar Description - ADC16DV160_14 |
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