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ADC16DV160 Datasheet(PDF) 1 Page - Texas Instruments |
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ADC16DV160 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 36 page ADC16DV160 www.ti.com SNAS488G – AUGUST 2009 – REVISED AUGUST 2011 ADC16DV160 Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs Check for Samples: ADC16DV160 1 FEATURES 2 • Low power consumption • 68-pin LLP package (10x10x0.8, 0.5mm pin- pitch) • On-chip precision reference and sample-and- hold circuit APPLICATIONS • On-chip automatic calibration during power-up • Multi-carrier, Multi-standard Base Station • Dual data rate LVDS output port Receivers • Dual Supplies: 1.8V and 3.0V operation – -MC-GSM/EDGE, CDMA2000, UMTS, LTE • Selectable input range: 2.4 and 2.0 VPP and WiMAX • Sampling edge flipping with clock divider by 2 • High IF Sampling Receivers option • Diversity Channel Receivers • Internal clock divide by 1 or 2 • Test and Measurement Equipment • On-chip low jitter duty-cycle stabilizer • Communications Instrumentation • Power-down and sleep modes • Portable Instrumentation • Output fixed pattern generation • Output clock position adjustment • 3-wire SPI • Offset binary or 2's complement data format DESCRIPTION The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 160 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and- hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16DV160 can be re-calibrated at any time through the 3-wire Serial Peripheral Interface (SPI). An integrated low noise and stable voltage reference and differential reference buffer amplifier eases board level design. The on-chip duty cycle stabilizer with low additive jitter allows a wide range of input clock duty cycles without compromising dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver block can be easily verified and optimized via fixed pattern generation and output clock position features. The digital data is provided via dual data rate LVDS outputs – making possible the 68-pin, 10 mm x 10 mm LLP package. The ADC16DV160 operates on dual power supplies of +1.8V and +3.0V with a power-down feature to reduce power consumption to very low levels while allowing fast recovery to full operation. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2009–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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