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ADC122S706 Datasheet(PDF) 8 Page - Texas Instruments |
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ADC122S706 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 31 page  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tACQ tCONV DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DOUTA SCLK CS 4 Leading Zeroes tPD Channel A Data DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DOUTB 4 Leading Zeroes Channel B Data tEN tDIS tCL tCH ADC122S706 SNAS408 – NOVEMBER 2007 www.ti.com ADC122S706 Timing Specifications (1) The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 MHz to 16 MHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits Units 5 11 ns (min) VD = +2.7V to 3.6V 1/ fSCLK 1/ fSCLK - 3 ns (max) tCSSU CS Setup Time prior to an SCLK rising edge 4 7 ns (min) VD = +4.5V to 5.5V 1/ fSCLK 1/ fSCLK - 3 ns (max) VD = +2.7V to 3.6V 22 39 ns (max) tEN DOUT Enable Time after the falling edge of CS VD = +4.5V to 5.5V 9 20 ns (max) tDH DOUT Hold time after an SCLK Falling edge 9 6 ns (min) VD = +2.7V to 3.6V 24 39 ns (max) tDA DOUT Access time after an SCLK Falling edge VD = +4.5V to 5.5V 20 26 ns (max) tDIS DOUT Disable Time after the rising edge of CS (2) 10 20 ns (max) tCH SCLK High Time 25 ns (min) tCL SCLK Low Time 25 ns (min) tr DOUT Rise Time 7 ns tf DOUT Fall Time 7 ns (1) Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis. (2) tDIS is the time for DOUT to change 10%. Timing Diagrams Figure 1. ADC122S706 Single Conversion Timing Diagram (DUAL Data Output Mode) 8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Links: ADC122S706 |
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