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DEM-ADS807E

CLOCK

The DEM-ADS807E requires an external TTL clock applied

at SMA connector J1. This input represents a 50

Ω load to the

source. In order to preserve the specified performance of the

ADS807E converter, the clock source should feature a very

low jitter. This is particularly important if the converter is to

be evaluated in an undersampling condition. The ADS807E

can accept logic HIGH levels as low as +2.7V. For best

performance results, a +3V logic HIGH voltage with rise

and fall times of 1

µs should be used.

EXTERNAL REFERENCE

The ADS807E can be operated with an external reference.

For this, solder switch ‘INT/EXT’ must be opened disabling

the internal references. Close solder switches JP3 and JP4

and apply the external reference voltage at connector P3.

The selected reference voltage determines the full-scale

input signal range of converter. However, the specified

range for external reference voltages should be observed

(see the ADS807 data sheet for details).

DATA OUTPUT

The data output is provided at CMOS logic levels. The

ADS807E uses Straight Offset Binary coding. The data

output pins of the converter are buffered from the I/O

connector, CN1, by two CMOS octal buffer (FCT541).

PC BOARD LAYOUT

The DEM-ADS807E demonstration board consists of a

four-layer PC board. To achieve the highest level of perfor-

mance, surface-mount components are used wherever pos-

sible. This reduces the trace length and minimizes the effects

of parasitic capacitance and inductance. The A/D converter

is treated like an analog component. Therefore, the demon-

stration board has one consistent ground plane. Keep in

mind that this approach may not necessarily yield optimum

performance results when designing the ADS807E into

different individual applications. In any case, thoroughly

bypassing the power supply and reference pins of the con-

verter, as demonstrated on the evaluation board, is strongly

recommended.