LMK03200

SNAS478B – JULY 2009 – REVISED AUGUST 2009

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Electrical Characteristics

(1) (continued)

(3.15 V

time of product characterization and are not guaranteed).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CLKoutX_MUX =

Bypass (no

20

divide or delay)

Distribution Path =

CLKoutX_MUX =

765 MHz

fs

Divided (no

Bandwidth =

delay)

75

12 kHz to 20 MHz

CLKoutX_DIV =

4

Differential Output Voltage

250

350

450

mV

-50

50

mV

complementary output states

Output Offset Voltage

1.070

1.25

1.370

V

-35

35

mV

complementary output states

Clock Output Short Circuit Current

Single-ended outputs shorted to GND

-24

24

mA

single-ended

Clock Output Short Circuit Current

Complementary outputs tied together

-12

12

mA

differential

CLKoutX_MUX =

Bypass (no

20

divide or delay)

Distribution Path =

CLKoutX_MUX =

765 MHz

fs

Divided (no

Bandwidth =

delay)

75

12 kHz to 20 MHz

CLKoutX_DIV =

4

Vcc -

Output High Voltage

V

0.98

Termination = 50

Ω to Vcc - 2 V

Vcc -

Output Low Voltage

V

1.8

Differential Output Voltage

660

810

965

mV

High-Level Input Voltage

2.0

Vcc

V

Low-Level Input Voltage

0.8

V

High-Level Input Current

-5.0

5.0

µA

Low-Level Input Current

-40.0

5.0

µA

Vcc -

High-Level Output Voltage

V

0.4

Low-Level Output Voltage

0.4

V

High-Level Input Voltage

1.6

Vcc

V

Low-Level Input Voltage

0.4

V

High-Level Input Current

-5.0

5.0

µA

Low-Level Input Current

-5.0

5.0

µA

(11) The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications

apply to the clock distribution section only and this adds in an RMS fashion to the shaped jitter of the PLL and the VCO.

(12) Applies to GOE, LD, and SYNC*.

(13) Applies to CLKuWire, DATAuWire, and LEuWire.

8

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