10

0.2

0

20

15

25

30

40

35

0.4

1.0

0.8

1.2

0.6

V

UDG-02132

Clock

PWM RAMP

PowerGood

VIN

UVLO Threshold

1 2 3 4 5 6 7

1 2 3 4 5 6 7

1 2

TPS40054

TPS40055

TPS40057

www.ti.com

SLUS593H – DECEMBER 2003 – REVISED JULY 2012

Figure 4. Undervoltage Lockout Operation

The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the

device at 10% below the nominal start-up voltage, the maximum duty cycle is reduced approximately 10% at the

nominal start-up voltage.

The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter

starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents

select the start-up voltage, the approximate amount of hysteresis voltage is shown in Figure 5.

UNDERVOLTAGE LOCKOUT THRESHOLD

vs

HSYTERESIS

Figure 5.

Copyright © 2003–2012, Texas Instruments Incorporated

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