TPS92075

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SLUSB88B – DECEMBER 2012 – REVISED JANUARY 2014

ABSOLUTE MAXIMUM RATINGS

(1)

terminal (unless otherwise noted)

VALUE

UNIT

MIN

MAX

Input voltage range

VCC

–0.3

22

V

ASNS, COFF

–0.3

6.0

Bias and ISNS

2.5

mA

–0.3

2.5

V

Gate

GATE - continuous

–0.3

18

V

GATE - 100 ns

–2.5

20.5

V

Continuous power dissipation

Internally Limited

Electrostatic discharge

Human Body Model (HBM)

2

kV

Field Induced Charged Device Model (FICDM)

750

V

(3)

160

°C

–65

150

°C

Lead temperature, soldering, 10s

260

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

ISNS can sustain –2 V for 100 ns without damage.

(3)

Maximum junction temperature is internally limited.

THERMAL INFORMATION

TPS92075

SOIC

TSOT

UNITS

(D)

(DDC)

8 PINS

6 PINS

112.3

165.5

58.4

28.8

52.5

24.6

°C/W

12.5

0.3

51.9

23.8

NA

NA

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-board characterization parameter,

from the simulation data for obtaining

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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