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LM2647 Datasheet(PDF) 5 Page - Texas Instruments

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Part # LM2647
Description  Dual Synchronous Buck Regulator Controller
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LM2647 Datasheet(HTML) 5 Page - Texas Instruments

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LM2647
www.ti.com
SNVS210E – MAY 2004 – REVISED JUNE 2005
Pin Description (continued)
Pin 20, LDRV2: Gate drive pin for the Channel 2 bottom FET (Low-side drive). The bottom gate driver is interlocked with the top gate driver
to prevent shoot-through/cross-conduction. It is always latched high when a fault condition is asserted by the IC.
Pin 21, V5: Upper rail of the lower FET drivers of both channels. Also used to charge up the bootstrap capacitors of the upper FET drivers.
This is connected to an external 5V supply. The 5V rail may be the same as the rail used to provide power to the VDD pin (Pin 5), but the
VDD pin will then require to be well-decoupled so that it does not interact with the V5 pin. A low-pass RC filter consisting of a ceramic 0.1µF
capacitor (preferably 0.22µF) and a 10
Ω resistor will suffice as shown in the Typical Applications circuit.
Pin 22, VIN: The input to both the Buck regulator power stages. It also is used by the internal ramp generator to implement the line
feedforward feature. The VIN pin is also used with the SENSE pin voltage to predict the CCM (continuous conduction mode) duty cycle and
to thereby set the minimum allowed DCM duty cycle to 85% of the CCM value (in SKIP mode, see Pin 10). This is a high input impedance
pin, drawing only about 100µA (typical) from the input rail.
Pin 23, LDRV1: LDRV pin of Channel 1. See Pin 20.
Pin 24, PGND1: PGND pin for Channel 1.See Pin 19.
Pin 25, BOOT1: Boot pin of Channel 1. See Pin 18.
Pin 26, HDRV1: HDRV pin of Channel 1. See Pin 17.
Pin 27, SW1: SW pin of Channel 1. See Pin 16.
Pin 28, ILIM1: Channel 2 Current Limit pin. See Pin 15.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)
Voltages from the indicated pins to SGND/PGND unless otherwise indicated (2):
VIN
30V
V5
7V
VDD
7V
BOOT1, BOOT2
36V
BOOT1 to SW1, BOOT2 to SW2
7V
SW1, SW2
30V
ILIM1, ILIM2
30V
SENSE1, SENSE2, FB1, FB2
7V
PGOOD
7V
EN
7V
Power Dissipation (TA = 25°C)
(3)
1.0W
Junction Temperature
+150°C
ESD Rating (Note 4)
2kV
Ambient Storage Temperature Range
-65°C to +150°C
Soldering Dwell Time, Temperature
Wave
4 sec, 260°C
Infrared
10 sec, 240°C
Vapor Phase
75 sec, 219°C
(1)
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is guaranteed. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics table.
(2)
PGND1, PGND2 and SGND are all electrically connected together on the PCB.
(3)
The maximum allowable power dissipation is calculated by using PDmax = (TJMAX - TA) /θJA , where TJMAX is the maximum junction
temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance of the specified package. The 1.0W
rating of the TSSOP-28 package for example results from using 125°C, 25°C, and 97°C/W for TJMAX, TA, and θJA respectively. The
2.85W rating of the 28-pin LLP package results from using 125°C, 25°C, and 35°C/W for TJMAX, TA, and θJA respectively. The rated
power dissipation should be derated by 10mW/°C above 25°C ambient for the TSSOP package and 29mW/°C above 25°C ambient for
the LLP package. The
θJA value above represents the worst-case condition with no heat sinking. Heat sinking will permit more power to
be dissipated at higher ambient temperatures. For detailed information on soldering plastic TSSOP and LLP packages, refer to
http://www.national.com/packaging/.
Copyright © 2004–2005, Texas Instruments Incorporated
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