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AMC1210 Datasheet(PDF) 9 Page - Texas Instruments |
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AMC1210 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 54 page  PARALLEL MODE 2 TIMING CHARACTERISTICS (1) ADDR ADDR ADDR+1 MSB LSB MSB t w1 t w2 t d1 t w3 t w4 t w5 t d4 t d3 t d2 AD(7:0) Internaladdress Parallelmode2,writeaccess CS WR RD ALE t su1 t h1 t su2 t h2 ADDR MSB LSB MSB ADDR ADDR+1 t d5 t d6 t w6 t w7 t d9 AD(7:0) Internaladdress Parallelmode2,readaccess CS WR RD ALE t d7 t d8 AMC1210 www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009 Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, and BVDD = +2.7V, unless otherwise noted. PARAMETER(2) MIN MAX UNIT tw1 CS low width 40 ns tw2 CS high width 5 ns td1 Delay time from ALE low to CS high 5 ns td2 Delay time from WR high to CS high 5 ns td3 Delay time from CS low to WR low 3 ns tw3 WR low width 10 ns tw4 WR high width 10 ns tw5 ALE high width 10 ns td4 Delay time from ALE low to WR low 10 ns tsu1 Setup time from address valid to ALE low 6 ns th1 Hold time from ALE low to address invalid 5 ns td5 Delay time from CS low to RD low 0 ns tsu2 Setup time from data valid to WR high 6 ns th2 Hold time from WR high to data invalid 5 ns td6 Delay time from RD high to CS high 6 ns tw6 RD low width 30 ns tw7 RD high width 13 ns td7 Delay time from RD low to data valid 30 ns td8 Delay time from RD high to databus in tristate 0 10 ns td9 Delay time from ALE low to RD low 10 ns (1) All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. (2) tw2 is obsolete if CS stays low between the WR, RD and ALE pulses. Figure 5. Parallel Mode 2 Timing Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): AMC1210 |
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