1394a-2000

Link Core

HSDI1

ISO

PORT

Ex-CPU

IF

M6/AES

Encryption /

decryption

logic

M6/AES

Encryption /

decryption

logic

ISO0

FIFO

4K

Bytes

ISO1

FIFO

4K

Bytes

PACKETIZER

(IEC61883 Isochronous,

Asynchronous,

Asynchronous Stream,

PHY Packets)

HSDI0

ISO

PORT

Async

TX0

FIFO

2K Bytes

Async

TX1

FIFO

2K Bytes

Async

RX0

FIFO

2K Bytes

Async

RX1

FIFO

2K Bytes

1394a-2000

PHY Core

2/3 ports

SELF ID

FIFO

1K Bytes

DMA

CFR

AKE CFR

LEB

HW

AKE

GPIO

1 or 8

16 or

32

MPEG2-DVB

1 or 8

DirecTV(DSS)

1 or 8

Digital Video (DV)

OR

OR

MPEG2-DVB

DirecTV(DSS)

Digital Video (DV)

OR

OR

TSB43Ex4x

www.ti.com

SLLA275C – APRIL 2008 – REVISED FEBRUARY 2010

BLOCK DIAGRAM

NOTE: Blocks with checked/shaded pattern are available only in selected versions of the device.

Copyright © 2008–2010, Texas Instruments Incorporated

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