TYPICAL DEVICE IMPLEMENTATION

3.3V

GPIO

10nF

10nF

10nF

10nF

10nF

10nF

10nF

10nF

N ote:

1) Place supply caps close to device pin

2) EN can be left open or tied to supply when no external control

is implem ented

3) Output pre-emphasis (D1, D0) is shown enabled . Setting will

depend on device placem ent relative to eSATA connector

EN

VCC

TX_0P

TX_0N

GND

VCC

RX_1P

RX_1N

GND

NC

D0

VCC

RX_0P

RX_0N

GND

VCC

TX_1P

TX_1N

GND

D1

1

10

20

11

SN75LVCP422DB

DETAILED DESCRIPTION

INPUT EQUALIZATION

OUTPUT PRE-EMPHASIS

LOW POWER MODE

SN75LVCP422

Each differential input of the SN75LVCP422 has 7 dB of fixed equalization in its front stage. The equalization

amplifies high frequency signals to correct for loss from the transmission channel. The input equalizer is

designed to recover signal even when no eye is present at the receiver and affectively supports FR4 trace at the

input anywhere from <4 inches to 20 inches or <10 cm to >50 cm.

The SN75LVCP422 provides single step pre-emphasis from 0 dB to 2.5 dB at each of its differential outputs.

Pre-emphasis is controlled independently for each channel and is set by the control pins D0 and D1 as shown in

Table 1. The pre-emphasis duration is 0.5 UI or 133 ps (typ) at SATA 3-Gbps speed.

Two low power modes are supported by the SN75LVCP422:

• Sleep Mode (triggered by EN pin, EN = 0 V)

–

Low power mode is controlled by the enable (EN) pin. In its default state this pin is internally pulled high.

Pulling this pin low puts the device in sleep mode within 2 us (max). In this mode all active components of

the device are driven to their quiescent level and differential outputs are driven to Hi-Z (open). Maximum

power dissipation in this mode is 5 mW. Exiting from this mode to normal operation requires a maximum

latency of 20

µs.

• Auto Low Power Mode (triggered when a given channel is in electrical idle state, EN = V

Copyright © 2009, Texas Instruments Incorporated

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Product Folder Link(s): SN75LVCP422