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TIMING CHARACTERISTICS

SWITCHING CHARACTERISTICS

SN65LVDS122

SN65LVDT122

SLLS525B – MAY 2002 – REVISED JUNE 2004

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Input to select setup time

0

ns

Input to select hold time

0.5

ns

Select to switch output

1

2

2.6

ns

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Propagation delay time, low-to-high-level output

400

650

900

ps

Propagation delay time, high-to-low-level output

400

650

900

ps

See Figure 4

Differential output signal rise time (20% - 80%)

280

ps

Differential output signal fall time (20% - 80%)

280

ps

(2)

10

50

ps

100

ps

1

2.2

ps

10

17

ps

33

65

ps

17

50

ps

Propagation delay time, high-level-to-high-impedance output

See Figure 5

6

8

ns

Propagation delay time, low-level-to-high-impedance output

See Figure 5

6

8

ns

Propagation delay time, high-impedance-to-high-level output

See Figure 5

4

6

ns

Propagation delay time, high-impedance-to-low-level output

See Figure 5

4

6

ns

15

40

ps

(1)

All typical values are at 25

°C and with a 3.3-V supply.

(2)

(3)

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(4)

Jitter is specified by design and characterization. Stimulus jitter has been subtracted.

(5)

(6)

(7)

(8)

(9)

Output skew is the magnitude of the time delay difference between the outputs of a single device with all inputs tied together.

4