MBM29LV320BE90PBT datasheet(2/64 Pages) FUJITSU

Part #	MBM29LV320BE90PBT

Description	32 M (4 M X 8/2 M X 16) BIT

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Manufacturer	FUJITSU [Fujitsu Component Limited.]

Direct Link	http://edevice.fujitsu.com/fmd/en/index.html

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MBM29LV320TE/BE80/90/10

2

(Continued)

The device is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the

command register using standard microprocessor write timings. Register contents serve as input to an internal

state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses

and data needed for the programming and erase operations. Reading data out of the device is similar to reading

from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded

Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies

proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is

accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which

is an internal algorithm that automatically preprograms the array if it is not already programmed before executing

the erase operation. During erase, the device automatically time the erase pulse widths and verify proper cell

margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The device is erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low VCC detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the device internally resets to the read mode.

The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program

Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read

mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the

Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode

and will have erroneous data stored in the address locations being programmed or erased. These locations

need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up

firmware from the Flash memory.

Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The device memory electrically erase the entire chip or all bits within

a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a

time using the EPROM programming mechanism of hot electron injection.

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MBM29LV320BE90PBT Datasheet(PDF) 2 Page - Fujitsu Component Limited.

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