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ADS1148IPW Datasheet(PDF) 3 Page - Texas Instruments |
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ADS1148IPW Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 67 page  (V )(Gain) IN 2 AVSS 0.1V + + AVDD 0.1V - - (V )(Gain) IN 2 ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at AVDD = +5V, DVDD = +3.3V, AVSS = DGND = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted. ADS1146, ADS1147, ADS1148 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage ±VREF/PGA (1) V (VIN = ADCINP – ADCINN) Common-mode input range V Differential input current 100 pA 1, 2, 4, 8, 16, 32, PGA gain settings 64, 128 Burnout current source 0.5, 2, or 10 μA Bias voltage (AVDD + AVSS)/2 V Bias voltage output impedance 400 Ω SYSTEM PERFORMANCE Resolution No missing codes 16 Bits 5, 10, 20, 40, 80, Data rate 160, 320, 640, SPS 1000, 2000 Integral nonlinearity (INL) Differential input, end point fit, PGA = 1 ±0.5 ±1 LSB Offset error After calibration 1 LSB PGA = 1 100 nV/°C Offset drift PGA = 128 15 nV/°C Gain error Excluding VREF errors ±0.5 % PGA = 1, excludes VREF drift 1 ppm/°C Gain drift PGA = 128, excludes VREF drift –3.5 ppm/°C ADC conversion time Single-cycle settling See Table 12 Noise See Table 1 and Table 2 Normal-mode rejection See Table 5 At dc, PGA = 1 90 dB Common-mode rejection At dc, PGA = 32 100 dB Power-supply rejection AVDD, DVDD at dc 100 dB VOLTAGE REFERENCE INPUT Voltage reference input (AVDD – 0.5 V (VREF = VREFP – VREFN) AVSS) – 1 Negative reference input (REFN) AVSS – 0.1 REFP – 0.5 V Positive reference input (REFP) REFN + 0.5 AVDD + 0.1 V Reference input current 30 nA ON-CHIP VOLTAGE REFERENCE Output voltage 2.038 2.048 2.058 V Output current(2) ±10 mA Load regulation 50 μV/mA Drift(3) TA = –40°C to +105°C 20 50 ppm/°C Startup time See Table 6 μs (1) For VREF > 2.7V, the analog input differential voltage should not exceed 2.7V/PGA (2) Do not exceed this loading on the internal voltage reference. (3) Specified by the combination of design and final production test. Copyright © 2009–2012, Texas Instruments Incorporated 3 |
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