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ADS7863ADBQ Datasheet(PDF) 6 Page - Texas Instruments |
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ADS7863ADBQ Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 42 page  ADS7863A SBAS610 – DECEMBER 2013 www.ti.com TIMING REQUIREMENTS (1) Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5 V, and BVDD = 2.7 V to 5 V, unless otherwise noted. PARAMETER COMMENTS MIN MAX UNIT tCONV Conversion time fCLOCK = 32 MHz 406.25 ns tACQ Acquisition time fCLOCK = 32 MHz 62.5 ns fCLOCK CLOCK frequency See Figure 2 1 32 MHz tCLOCK CLOCK period See Figure 2 31.25 1000 ns tCKL CLOCK low time See Figure 2 9.4 ns tCKH CLOCK high time See Figure 2 9.4 ns t1 CONVST high time See Figure 2 20 ns t2 SDI setup time to CLOCK falling edge See Figure 2 10 ns t3 SDI hold time to CLOCK falling edge See Figure 2 5 ns t4 RD high setup time to CLOCK falling edge See Figure 2 10 ns t5 RD high hold time to CLOCK falling edge See Figure 2 5 ns t6 CONVST low time See Figure 2 1 tCLOCK t7 RD low time relative to CLOCK falling edge See Figure 2 1 tCLOCK t8 CS low to SDOx valid See Figure 2 13 ns See Figure 2, 4 11 ns CLOCK rising edge to DATA valid delay 2.7 V ≤ BVDD ≤ 3.6 V t9 (MIN = minimum hold time of current data; See Figure 2, MAX = maximum delay to new data valid) 3 9 ns 4.5 V ≤ BVDD ≤ 5.5 V t10 CONVST rising edge to BUSY high delay(2) See Figure 2 3 ns t11 CLOCK rising edge to BUSY low delay See Figure 2 3 ns t12 CS low to RD high delay See Figure 2 10 ns (1) All input signals are specified with tR = tF = 1.5 ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH) / 2. (2) Not applicable in auto-NAP power-down mode. 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS7863A |
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