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ADS1293 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS1293 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 76 page ADS1293 www.ti.com SNAS602B – FEBRUARY 2013 – REVISED MARCH 2013 TIMING DIAGRAMS Unless otherwise noted, all limits specified at TA = 25°C, +2.7V ≤ VDD ≤ +5.5V, +1.65 ≤ VDDIO ≤ MIN(+3.6V, VDD), VREF = +2.4V, fOSC = 409.6kHz and a 10pF capacitive load in parallel with a 10kΩ load on SDO. Figure 1. Write Timing Diagram PARAMETER CONDITIONS MIN TYP MAX UNIT FSCLK Serial Clock Frequency 20 MHz tPH SCLK Pulse Width - High FSCLK = 20MHz 0.4/FSCLK s tPL SCLK Pulse Width - Low FSCLK = 20MHz 0.4/FSCLK s tSU SDI Setup Time 5 ns tH SDI Hold Time 5 ns Figure 2. Read Timing Diagram PARAMETER CONDITIONS MIN TYP MAX UNIT tODZ SDO Driven-to-Tristate Time Measured at 10% / 90% point 15 ns tOZD SDO Tristate-to-Driven Time Measured at 10% / 90% point 15 ns tOD SDO Output Delay Time 10 ns tCSS CSB Setup Time 5 ns tCSH CSB Hold Time 5 ns tIAG Inter-Access Gap 10 ns tDRDYB Data Ready Bar at every 1/ODR second, see 4/fOSC s Figure 25 Copyright © 2013, Texas Instruments Incorporated 9 Product Folder Links: ADS1293 |
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