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AK4161 Datasheet(PDF) 8 Page - Asahi Kasei Microsystems |
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AK4161 Datasheet(HTML) 8 Page - Asahi Kasei Microsystems |
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8 / 12 page  [AK4161] MS1450-E-02-PB 2014/05 - 8 - SWITCHING CHARACTERISTICS (Ta = -40C ~ 85C, VDD = 1.6V ~ 3.6V; unless otherwise specified) Parameter Symbol min typ max Unit Internal Oscillator Fast Oscillator Period FPRD 75 125 175 ns Slow Oscillator Period SPRD 21 32 43 us Reset Timing Reset Pulse Width (Note 15) tRW 10 - - us Reset Pin Pulse Width of Spike Noise Suppressed by Input Filter (Note 16) tRS 0.5 - - us I2C SCL clock frequency fSCL - - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - us Start Condition Hold Time (prior to first Clock pulse) tHD:STA 0.6 - - us Clock Low Time tLOW 1.3 - - us Clock High Time tHIGH 0.6 - - us Setup Time for Repeated Start Condition tSU:STA 0.6 - - us SDA Hold Time from SCL Falling (Note 17) tHD:DAT 0 - - us SDA Setup Time from SCL Rising tSU:DAT 0.1 - - us Rise Time of Both SDA and SCL Lines tR - - 0.3 us Fall Time of Both SDA and SCL Lines tF - - 0.3 us Setup Time for Stop Condition tSU:STO 0.6 - - us Pulse Width of Spike Noise Suppressed By Input Filter tSP 50 - - ns Capacitive load on bus Cb - - 400 pF Note 15. The AK4161 can be reset by the RSTN pin = “L”. Keep “L” period for 10us or more for a certain reset. Note 16. Pulse width of spike noise suppressed by input filter of the RSTN pin. Note 17. Data must be held for sufficient time to bridge the 300ns transition time of SCL. RSTN tRW tRS 50%VDD Figure 2. Reset Timing Diagram tHIGH SCL SDA VIH tLOW tBUF tHD:STA tR tF tHD:DAT tSU:DAT tSU:STA Stop Start Start Stop tSU:STO VIL VIH VIL tSP Figure 3. I 2C Interface Timing Diagram |
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Similar Description - AK4161 |
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