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ADC10040QCIMTX Datasheet(PDF) 3 Page - Texas Instruments |
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ADC10040QCIMTX Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 28 page  ADC10040 www.ti.com SNAS224M – JULY 2003 – REVISED APRIL 2013 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O Inverting analog input signal. With a 1.2V reference the full-scale 12 VIN− input signal level is a differential 1.0 VP-P. This pin may be tied to VCOM (pin 4) for single-ended operation. Non-inverting analog input signal. With a 1.2V reference the full- 13 VIN+ scale input signal level is a differential 1.0 VP-P. Reference Voltage. This device provides an internal 1.2V reference. This pin should be bypassed to VSSA with a 0.1 µF monolithic 6 VREF capacitor. VREF is 1.20V nominal. This pin may be driven by a 1.20V external reference if desired. Do not load this pin. 7 VREFT These pins are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to VSSA. These pins 4 VCOM should not be loaded. VCOM may be used to set the input common mode voltage VCM. 8 VREFB DIGITAL I/O Digital clock input. The range of frequencies for this input is 20 MHz 1 CLK to 40 MHz. The input is sampled on the rising edge of this input. DF = “1” Two’s Complement 15 DF DF = “0” Offset Binary This is the standby pin. When high, this pin sets the converter into 28 STBY standby mode. When this pin is low, the converter is in active mode. IRS = “VDDA” 2.0 VP-P input range IRS = “VSSA” 1.5 VP-P input range IRS (Input Range 5 IRS = “Floating” 1.0 VP-P input range Select) If using both VIN+ and VIN- pins, (or differential mode), then the peak-to-peak voltage refers to the differential voltage (VIN+ - VIN-). Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC10040 |
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