Electronic Components Datasheet Search |
|
ADS62P24 Datasheet(PDF) 10 Page - Texas Instruments |
|
ADS62P24 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 78 page ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) Typical values are specified at 25 °C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), I O = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V, unless otherwise specified. FS = 65 MSPS FS = 40 MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX PARALLEL CMOS INTERFACE, DRVDD = 1.8 V, MULTIPLEXED MODE, maximum buffer drive strength (4) Input clock falling edge to tSTART_CHA channel A data getting valid (5) 0.8 2.3 8 9.5 ns (6) tDV_CHA Width of valid data window 5.4 6.4 10.3 11.3 ns Input clock falling edge to tSTART_CHB channel A data getting valid (5) 1.1 2.4 8.4 9.7 ns (6) tDV_CHB Width of valid data window 5 6 9.7 10.7 ns (1) Timing parameters are specified by design and characterization and not tested in production. (2) CL is the effective external single-ended load capacitance between each output pin and ground. (3) IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. (4) For DRVDD < 2.2 V, output clock cannot be used for data capture. A delayed version of the input clock can be used, that gives the desired setup and hold times at the receiving chip (5) Data valid refers to logic high of 1.26V and logic low of 0.54V for DRVDD = 1.8V. (6) Measured from zero-crossing of input clock having 50% duty cycle. Table 2. Timing Characteristics at Lower Sampling Frequencies SAMPLING tPDI CLOCK PROPAGATION DELAY, FREQUENCY, tsu DATA SETUP TIME, ns th DATA HOLD TIME, ns ns MSPS MIN TYP MAX MIN TYP MAX MIN TYP MAX CMOS INTERFACE, DRVDD = 2.5 V TO 3.6 V 40 10.5 12 10.3 11.8 5.8 7.3 8.8 20 23 24.5 23 24.5 LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V 40 8.5 10 1 2.3 3.5 5.5 7.5 20 21 22.5 1 2.3 10 Copyright © 2007–2011, Texas Instruments Incorporated |
Similar Part No. - ADS62P24_14 |
|
Similar Description - ADS62P24_14 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |