ADCS7476, ADCS7477, ADCS7478

SNAS192F – APRIL 2003 – REVISED MARCH 2013

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ADCS7476/ADCS7477/ADCS7478 Specifications

(1)

ADCS7478 Converter Electrical Characteristics (continued)

Symbol

Parameter

Conditions

Typical

Limits

Units

Output High Voltage

V (min)

Output Low Voltage

0.4

V (max)

TRI-STATE Leakage Current

±10

µA (max)

TRI-STATE Output Capacitance

2

4

pF (max)

Output Coding

Straight (Natural) Binary

AC ELECTRICAL CHARACTERISTICS

Clock Frequency

20

MHz (max)

40

% (min)

DC

SCLK Duty Cycle

60

% (max)

Track/Hold Acquisition Time

400

ns (max)

Throughput Rate

See Applications Information

1

MSPS (min)

Aperture Delay

3

ns

Aperture Jitter

30

ps

Figure 2. Timing Test Circuit

Timing Test Circuit ADCS7476/ADCS7477/ADCS7478 Timing Specifications

(1)

Symbol

Parameter

Conditions

Typical

Limits

Units

(2)

50

ns (min)

Minimum CS Pulse Width

10

ns (min)

CS to SCLK Setup Time

10

ns (min)

Delay from CS Until SDATA TRI-STATE

20

ns (max)

40

ns (max)

Data Access Time after SCLK Falling

20

ns (max)

0.4 x

SCLK Low Pulse Width

ns (min)

0.4 x

SCLK High Pulse Width

ns (min)

7

ns (min)

SCLK to Data Valid Hold Time

5

ns (min)

(1)

(2)

Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion

(3)

Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V.

(4)

Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V.

8

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