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ADS1217IPFBRG4 Datasheet(PDF) 7 Page - Texas Instruments |
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ADS1217IPFBRG4 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 34 page  ADS1217 SBAS260C 7 www.ti.com SPEC DESCRIPTION MIN MAX UNITS t1 SCLK Period 4tOSC Periods 3 DRDY Periods t2 SCLK Pulse Width, HIGH and LOW 200 ns t3 CS LOW to First SCLK Edge; Setup Time(1) 0ns t4 DIN Valid to SCLK Edge; Setup Time 50 ns t5 Valid DIN to SCLK Edge; Hold Time 50 ns t6 Delay Between Last SCLK Edge for DIN and First SCLK Edge for DOUT: RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 tOSC Periods CSREG, CSRAMX, CSRAM 200 tOSC Periods CSARAM, CSARAMX 1100 tOSC Periods t7(2) SCLK Edge to Valid New DOUT 50 ns t8(2) SCLK Edge to DOUT, Hold Time 0 ns t9 Last SCLK Edge to DOUT Tri-State 6 10 tOSC Periods NOTE: DOUT goes tri-state immediately when CS goes HIGH. t10 CS LOW Time After Final SCLK Edge 0 ns t11 Final SCLK Edge of One Op Code Until First Edge SCLK of Next Command: RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, tOSC Periods CSRAM, CSARAM, CSREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC 4 tOSC Periods CREG, CRAM 220 tOSC Periods CREGA 1600 tOSC Periods SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY Periods SELFCAL 14 DRDY Periods RESET (Input pin, command, or SCLK pattern) 16 tOSC Periods t12 300 500 tOSC Periods t13 5tOSC Periods t14 550 750 tOSC Periods t15 1050 1250 tOSC Periods t16 Pulse Width 4tOSC Periods t17 Data Not Valid 4 tOSC Periods NOTES: (1) CS may be tied LOW. (2) Load = 20pF. TIMING DIAGRAMS TIMING CHARACTERISTICS t 4 MSB (Command or Command and Data) LSB t 5 t 1 t 3 CS SCLK (POL = 0) D IN D OUT NOTE: (1) Bit Order = 0. SCLK Reset Waveform t 7 MSB(1) LSB(1) t 8 t 10 t 2 t 2 t 11 t 6 t 9 SCLK (POL = 1) t 12 t 14 t 15 t 13 t 13 SCLK t 17 DRDY t 16 RESET, DSYNC, PDWN ADS1217 Resets On Falling Edge |
Similar Part No. - ADS1217IPFBRG4 |
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Similar Description - ADS1217IPFBRG4 |
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