ADC0801, ADC0802

ADC0803, ADC0804, ADC0805

SNOSBI1B – NOVEMBER 2009 – REVISED FEBRUARY 2013

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AC ELECTRICAL CHARACTERISTICS

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

(1)

103

114

µs

Conversion Time

66

73

1/fCLK

Clock Frequency

100

640

1460

kHz

(2)

Clock Duty Cycle

40%

60%

INTR tied to WR with CS = 0 VDC,

CR

Conversion Rate in Free-Running Mode

8770

9708

conv/s

Width of WR Input (Start Pulse Width)

100

ns

Access Time (Delay from Falling Edge of RD

tACC

135

200

ns

to Output Data Valid)

t1H, t0H

125

200

ns

RD to Hi-Z State)

TEST CIRCUITS AND WAVEFORMS)

Delay from Falling Edge of WR or RD to Reset

300

450

ns

of INTR

Input Capacitance of Logic Control Inputs

5

7.5

pF

TRI-STATE Output Capacitance (Data Buffers)

5

7.5

pF

CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]

2

15

0.8

Logical “1” Input Current (All Inputs)

0.005

1

Logical “0” Input Current (All Inputs)

–1 –0.005

CLOCK IN AND CLOCK R

CLK IN (Pin 4) Positive Going Threshold

2.7

3.1

3.5

Voltage

CLK IN (Pin 4) Negative Going Threshold

1.5

1.8

2.1

Voltage

0.6

1.3

2

Logical “0” CLK R Output Voltage

0.4

Logical “1” CLK R Output Voltage

2.4

DATA OUTPUTS AND INTR

Logical “0” Output Voltage

Data Outputs

0.4

INTR Output

0.4

2.4

Logical “1” Output Voltage

4.5

–3

TRI-STATE Disabled Output Leakage (All Data

Buffers)

3

4.5

6

9

16

POWER SUPPLY

Supply Current (Includes Ladder Current)

ADC0801/02/03/04LCJ/05

1.1

1.8

mA

ADC0804LCN/LCWM

1.9

2.5

mA

(1)

limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.

(2)

With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the

conversion process. The start request is internally latched, see Figure 48 and FUNCTIONAL DESCRIPTION.

(3)

The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide

pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse

(see TIMING DIAGRAMS).

4

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