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ADC122S655CIMM Datasheet(PDF) 5 Page - Texas Instruments |
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ADC122S655CIMM Datasheet(HTML) 5 Page - Texas Instruments |
5 / 28 page ADC122S655 www.ti.com SNAS445A – FEBRUARY 2008 – REVISED MARCH 2013 ADC122S655 Converter Electrical Characteristics (1) (continued) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 6.4 to 16 MHz, fIN = 100 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C. Symbol Parameter Conditions Typical Limits Units POWER SUPPLY CHARACTERISTICS 4.5 V (min) VA Analog Supply Voltage 5.5 V (max) IVA Analog Supply Current, fSCLK = 16 MHz, fS = 500 kSPS, fIN = 20 kHz, 2.2 2.75 mA (max) (Conv) Continuously Converting VA = 5V IVREF Reference Current, Continuously fSCLK = 16 MHz, fS = 500 kSPS, VREF = 2.5V 50 60 µA (max) (Conv) Converting fSCLK = 16 MHz, VA = 5.0V 15 µA Analog Supply Current, Power Down IVA (PD) Mode (CS high) fSCLK = 0, VA = 5.0V (2) 0.5 1.1 µA (max) fSCLK = 16 MHz, VREF = 2.5V 0.05 µA IVREF Reference Current, Power Down (PD) Mode (CS high) fSCLK = 0, VREF = 2.5V (2) 0.05 0.1 µA (max) PWR Power Consumption, Continuously fSCLK = 16 MHz, fS = 500 kSPS, fIN = 20 kHz, 11.1 13.9 mW (max) (Conv) Converting VA = 5.0V, VREF = 2.5V fSCLK = 16 MHz, VA = 5.0V, VREF = 2.5V 75 µW PWR Power Consumption, Power Down (PD) Mode (CS high) fSCLK = 0, VA = 5.0V, VREF = 2.5V 2.6 5.8 µW (max) See the Specification Definitions for the test PSRR Power Supply Rejection Ratio −85 dB condition AC ELECTRICAL CHARACTERISTICS fSCLK Maximum Clock Frequency 20 16 MHz (min) fSCLK Minimum Clock Frequency 1.6 6.4 MHz (max) Maximum Sample Rate(3) 625 500 kSPS (min) fS Minimum Sample Rate 50 200 kSPS (min) tACQ Track/Hold Acquisition Time 3 SCLK cycles tCONV Conversion Time 12 SCLK cycles tAD Aperture Delay 6 ns (2) Specified by design, characterization, or statistical analysis and is not tested at final test. (3) While the maximum sample rate is fSCLK/32, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/32. ADC122S655 Timing Specifications (1) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 6.4 MHz to 16 MHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits Units 4 7 ns (min) tCSSU CS Setup Time prior to an SCLK rising edge 1/ fSCLK 1/ fSCLK - 3 ns (max) tEN DOUT Enable Time after the falling edge of CS 9 20 ns (max) tDH DOUT Hold time after an SCLK Falling edge 9 6 ns (min) tDA DOUT Access time after an SCLK Falling edge 20 26 ns (max) tDIS DOUT Disable Time after the rising edge of CS (2) 10 20 ns (max) tCH SCLK High Time 25 ns (min) tCL SCLK Low Time 25 ns (min) tr DOUT Rise Time 7 ns tf DOUT Fall Time 7 ns (1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level). (2) tDIS is the time for DOUT to change 10%. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC122S655 |
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