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ADC122S021 Datasheet(PDF) 6 Page - Texas Instruments |
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ADC122S021 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 27 page IOL 200 PA IOH 200 PA 1.6V To Output Pin CL 35 pF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 Track Hold Power Up Track Hold b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 9 10 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB11 DB10 DB9 DB8 DB7 DIN DOUT Power Up SCLK CS Power Down Control register Control register ADC122S021 SNAS280D – MARCH 2005 – REVISED MARCH 2013 www.ti.com ADC122S021 TIMING SPECIFICATIONS (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, CL = 35 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits (1) Units 0.3 x tCL SCLK Low Pulse Width 0.5 x tSCLK ns (min) tSCLK VA = +3.0V 1.8 Output Falling VA = +5.0V 1.3 tDIS CS Rising Edge to DOUT High-Impedance 20 ns (max) VA = +3.0V 1.0 Output Rising VA = +5.0V 1.0 Timing Diagrams Figure 1. ADC122S021 Operational Timing Diagram Figure 2. Timing Test Circuit 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC122S021 |
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