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TLC3574IDWR Datasheet(PDF) 2 Page - Texas Instruments |
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TLC3574IDWR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 50 page TLC3574, TLC3578, TLC2574, TLC2578 5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS SLAS262C − OCTOBER 2000 − REVISED MAY 2003 2 WWW.TI.COM description (continued) In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by a special pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3574/78 and TLC2574/78 are designed to operate with low-power consumption. The power saving feature is further enhanced with autopower-down mode and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3574/78 and TLC2574/78 are specified with bipolar input and a full scale range of ±10 V. AVAILABLE OPTIONS PACKAGED DEVICES TA 20-TSSOP (PW) 20-SOIC (DW) 20-PDIP (N) 24-SOIC (DW) 24-TSSOP (PW) −40 °C to 85°C TLC2574IPW TLC2574IDW TLC2574IN TLC2578IDW TLC2578IPW −40 °C to 85°C TLC3574IPW TLC3574IDW TLC3574IN TLC3578IDW TLC3578IPW functional block diagram Analog MUX Signal Scaling Command Decode CMR (4 MSBs) SAR ADC OSC Conversion Clock FIFO X8 Control Logic 4-Bit Counter SDO EOC/INT DVDD AVDD DGND AGND CSTART FS CS SCLK SDI CFR REFM COMP REFP X8† A0 A1 A2 A3 A4 A5 A6 A7 X4‡ A0 A1 A2 A3 X X X X † TLC3578, TLC2578 ‡ TLC3574, TLC2574 NOTE: 4-Bit counter counts the CLOCK, SCLK. The CLOCK is gated in by CS falling edge if CS initiates the conversion operation cycle, or gated in by the rising edge of FS if FS initiates the operation cycle. SCLK is disabled for serial interface when CS is high. |
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