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TLV571IPWG4 Datasheet(PDF) 7 Page - Texas Instruments |
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TLV571IPWG4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 30 page TLV571 2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 start of conversion mechanism There are two ways to convert data: hardware and software. In the hardware conversion mode the ADC begins sampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software start mode ADC samples for 6 clocks, then conversion occurs for ten clocks. The total sampling and conversion process lasts only 16 clocks in this case. If RD is not detected during the next clock cycle, the ADC automatically proceeds to a power-down state. Data is valid on the rising edge of INT in both conversion modes. hardware CSTART conversion external clock With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART and conversion begins at the rising edge of CSTART. At the end of conversion, EOC goes from low to high, telling the host that conversion is ready to be read out. The external clock is active and is used as the reference at all times. With this mode, it is required that CSTART is not applied at the rising edge of the clock (see Figure 4). |
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