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TLV1504IPW Datasheet(PDF) 4 Page - Texas Instruments |
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TLV1504IPW Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 48 page  TLV1504, TLV1508 2.7V TO 5.5V, 10BIT, 200KSPS, 4/8CHANNEL, LOW POWER SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION NAME TLV1504 TLV1508 I/O DESCRIPTION SDO 1 1 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high and after the CS falling edge and until the MSB is presented. The output format is MSB first. When FS is not used (FS = 1 at the falling edge of CS), the MSB is presented to the SDO pin after the CS falling edge, and successive data are available at the rising edge of SCLK and changed on the falling edge. When FS is used (FS = 0 at the falling edge of CS), the MSB is presented to SDO after the falling edge of CS and FS = 0 is detected. Successive data are available at the falling edge of SCLK and changed on the rising edge. (This is typically used with an active FS from a DSP.) For conversion and FIFO read cycles, the first 12 bits are result from previous conversion (data) followed by 4 don’t care bits. The first four bits from SDO for CFR read cycles should be ignored. The register content is in the last 12 bits. SDO is 3-state (float) after the 16th bit. See the date code information section, item (2). REFM 14 18 I External reference input or internal reference decoupling. Tie this pin to analog ground if internal reference is used. REFP 15 19 I External reference input or internal reference decoupling. (Shunt capacitors of 10 µF and 0.1 µF between REFP and REFM.) The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the REFM terminal when an external reference is used. VCC 5 5 I Positive supply voltage detailed description analog inputs and internal test voltages The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching. converter The TLV1504/48 uses a 10-bit successive approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a simplified version of the ADC. The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the ADC output code is generated. |
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