TLV1578IDA datasheet(5/34 Pages) TI1

Part #	TLV1578IDA

Description	2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

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TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170D –MARCH 1999 – REVISED JULY 2000

5

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

detailed description (continued)

control registers

Output =

0:

Binary

1:

2s

Complement

0:

Reserved

Bit,

Always

Write 0

0:

INT. OSC.

SLOW

1:

INT. OSC.

FAST

7h

6h

5h

STARTSEL

A1

A0

D6

D5

D4

D3

D2

D1

D0

D7

Control Register Zero (CR0)

D6

D7

D5

D4

D3

D2

D1

D0

Channels Swept

PROGEOC

CLKSEL

SWPWDN

MODESEL

CHSEL(2–0)†

0:

HARDWARE

START

(CSTART)

A(1:0)=00

1:

SOFTWARE

START

0:

INT

1:

EOC

0:

Internal

Clock

1:

External

Clock

0:

NORMAL

1:

Power

Down

0:

Single

Channel

1:

Sweep

Mode

D(2– 0)

0h

1h

2h

3h

4h

0,1

0,1,2,3

0,1,2,3,4,5,

0,1,2,3,4,5,6,7

N/A

3h

2h

1h

RESERVED

Control Register One (CR1)

D6

D7‡

D3

D2

D1

D0

IF READREG = 0

OSCSPD

0 Reserved 0 Reserved

OUTCODE

READREG

0:

Reserved

Bit

Always

Write 0

A(1:0)=01

0:

Reserved

Bit

Always

Write 0

0:

Enable Self

Test

ACTION

1:

Enable

Register

Read back

0h

1h

2h

3h

CONVERSION result

SELF TEST 1 result

SELF TEST 2 result

Output Contents of

CR1

RESERVED

STEST1

STEST0

CR1.(1–0)

SELF TEST 3 result

IF READREG = 1

Output Contents of

CR0

0h

7

6

5

Single

Input

0

1

2

3

4

Output =

D5‡

D4‡

† Don’t care for TLV1571

‡ When in read back mode, the values read from the control register reserved bits are don’t care.

Figure 2. Input Data Format

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