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ADC12DL040 Datasheet(PDF) 5 Page - Texas Instruments |
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ADC12DL040 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 38 page  VDR DR GND AGND VA VD DGND AGND VA VD DGND AGND VA ADC12DL040 www.ti.com SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013 Pin No. Symbol Equivalent Circuit Description DIGITAL I/O Digital clock input. The range of frequencies for this input is as 60 CLK specified in the electrical tables with ensured performance at 40 MHz. The input is sampled on the rising edge. OEA and OEB are the output enable pins that, when low, holds their respective data output pins in the active state. When either of these pins is high, the corresponding outputs are in a high impedance state. 22 OEA 41 OEB PD is the Power Down input pin. When high, this input puts the 59 PD converter into the power down mode. When this pin is low, the converter is in the active mode. When low, "A" and "B" data is present on it's respective data output lines (Parallel Mode). When high, both "A" and "B" channel data is present on the "DA0:DA11" digital outputs (Multiplex Mode). The DB0/ABb pin is used to synchronize the data. 11 MULTIPLEX 24–29 Digital data output pins that make up the 12-bit conversion results of DA0–DA11 34–39 their respective converters. DA0 and DB0 are the LSBs, while DA11 and DB11 are the MSBs of the output word. Output levels are 43–47 DB1–DB11 TTL/CMOS compatible. Optimum loading is < 10pF. 52–57 When MULTIPLEX is low, this is DB0. When MULTIPLEX is high this is the ABb signal, which is used to 42 DB0/ABb synchronize the multiplexed data. ABb changes synchronously with the Multiplexed "A" and "B" channels. ABb is "high" when "A" channel data is valid and is "low" when "B" channel data is valid. ANALOG POWER Positive analog supply pins. These pins should be connected to a 9, 18, 19, 62, VA quiet +3.0V source and bypassed to AGND with 0.1 µF capacitors 63 located within 1 cm of these power pins, and with a 10 µF capacitor. 3, 8, 10, 17, AGND The ground return for the analog supply. 20, 61, 64 DIGITAL POWER Positive digital supply pin. This pin should be connected to the same quiet +3.0V source as is VA and be bypassed to DGND with a 0.1 µF 33, 48 VD capacitor located within 1 cm of the power pin and with a 10 µF capacitor. 32, 49 DGND The ground return for the digital supply. Positive driver supply pin for the ADC12DL040's output drivers. This pin should be connected to a voltage source of +2.4V to VD and be bypassed to DR GND with a 0.1 µF capacitor. If the supply for this 30, 51 VDR pin is different from the supply used for VA and VD, it should also be bypassed with a 10 µF capacitor. VDR should never exceed the voltage on VD. All 0.1 µF bypass capacitors should be located within 1 cm of the supply pin. The ground return for the digital supply for the ADC12DL040's output drivers. These pins should be connected to the system digital 23, 31, 40, DR GND ground, but not be connected in close proximity to the 50, 58 ADC12DL040's DGND or AGND pins. See LAYOUT AND GROUNDING for more details. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC12DL040 |
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