TLV1562

2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL

CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN

SLAS162 – SEPTEMBER 1998

1

POST OFFICE BOX 655303

Channel),

±1 LSB DNL, ±1 LSB INL MAX

Channel),

±1 LSB DNL, ±1 LSB INL MAX

Channel),

±0.4 LSB DNL, ±0.4 LSB INL MAX

15 MHz at 5.5 V, 12 MHz at 2.7 V

–70.8 dB, THD –68.8 dB, at fi = 800 kHz,

10 Bit

(75 MHz at 1 dB, >120 MHz at –3 dB) at

(1

µA), Auto Powerdown (120 µA)

5.5 VDC

7 mA at 2.7 V, 8 MHz Operating

Dual Sample and Hold Matched Channels

Multi Chip Simultaneous Sample and Hold

Capable

Interrupt-Driven for Shorter Latency

Continuous Modes Optimized for MIPS

Sensitive DSP Solutions

Calibration

Single-Ended Input Channels

1 pF Max Switching)

applications

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CSTART

(LSB) D0

D1

D2

D3

D4

BDGND

D5

D6

D7

D8

(MSB) D9

INT

RD

AP/CH1

AM/CH2

BP/CH3

BM/CH4

VREFP

VREFM

AGND

WR

DGND

CLKIN

CS/OE

DW OR PW PACKAGE

(TOP VIEW)

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.