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ISL6295CVZ Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6295CVZ Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 25 page  9 FN9074.2 February 8, 2011 in Sample mode as long as "Samp" bit equals ‘1’, the VP voltage is above the VPOR threshold, and the Sample-Sleep and Shelf-Sleep modes are not active. Run mode will be resumed when the Samp bit is cleared to ‘0’. The Sample mode rate is selected using the "SampDiv" bits within the A/D Configuration Register. The sample interval is given by (2SampDiv x 0.5) sec. The possible sample rate intervals are as follows: In Sample mode, much of the analog circuitry remains on. Therefore, the power savings is not as great as in Sample- Sleep Mode described below. SAMPLE-SLEEP MODE In Sample-Sleep Mode, the ISL6295 goes into sleep mode and wakes up at a user-programmed interval to perform a set of conversions as programmed for the A/D cycle. The purpose of Sample-Sleep is to achieve the minimum power consumption possible while periodically measuring specified parameters. While the ISL6295 is in the sleep portion of the Sample-Sleep interval, all of the analog circuitry is shut off, and the Sleep interval time is derived from a less accurate ultra low power on- chip oscillator that is separate from the primary oscillator. During the active portion of Sample-Sleep Mode, a single set of conversions is performed and RUN mode current will be consumed for the duration of the measurements. While in Sample-Sleep mode, the accumulation counters and timers will still continue to run at an uninterrupted rate of 0.5s per update. Sample-Sleep Mode is invoked by one of the following actions: 1. Cell voltage on VP drops below the trip point programmed in the VCtrip register with the corresponding "VPent" bit set in the TRIPctrl register (If GPAD is grounded). This action can be used to prevent excessive battery discharge in the event of a dangerously low cell voltage. 2. If GPAD is used for other analog input, the GPAD voltage drops below the trip ponit programmed in the VCtrip register with the corresponding “GPADent” bit set in the TRIPctrl register. 3. Setting the “SSLP” bit in the OpMode register. The host can take this action when the system is entering a low power standby condition, and it is desireable to periodically update measurements for current, voltage, and/or temperature accumulation. 4. Magnitude of current measurement is less than the I-trip register value when "Ient" bit is set in the Tripctrl register. The Sample-Sleep interval is determined by the programming of the "SampDiv" bits within the ADconfig register, together with the "SSLPdiv" bits within the OpMode register. The sample interval is 2SampDivx 2SSLPdivx 0.5sec. The possible Sample- Sleep interval time therefore ranges from a minimum of 0.5sec to over 136 minutes. Exit from Sample-Sleep Mode to Run mode can be accomplished by clearing the "SSLP" bit or by programming a wake up based on pack voltage or current. Wake up based on charge current will occur when the "Iex" bit is set in the TRIPcntl register and the charging current value is above the threshold programmed in the I+trip register. Wake up based on pack voltage will occur when the "VPex" bit is set in the TRIPctrl register and the pack voltage rises above the threshold programmed in the VPtrip register. SHELF-SLEEP MODE Shelf-Sleep Mode is the lowest power mode and is intended to preserve battery capacity when the battery pack is shipped or stored or if the battery voltage drops below a specified threshold. While in Shelf-Sleep mode, no ADC measurement is taken, no accumulation is performed, and no SMBus communications are recognized. In addition, volatile memory is not maintained. Entry to Shelf-Sleep Mode is enabled by programming the “SHELF” bit in the OPmode register to ‘1’ or "Shent" bit in the TRIPctrl register to ‘1’ and when VP is less than SStrip. The Shelf Sleep mode will then be entered when the SMBus pins (both SDA and SCL) drop from a high to a low level for a minimum time period specified by tSHELF. This action will also occur if the battery pack is physically disconnected from the system. Exit from the Shelf-Sleep mode back to Run mode will occur when the SMBus pins (both SDA and SCL) are both pulled from a low to a high state, and remain high for a minimum time of tWAKE to signify system activity or connection of the pack to the host. General Purpose Input/Output The NTC and GPAD pins have alternate functions of general purpose I/O. IO0 and IO1 respectively. These pins can be configured as digital General Purpose Inputs/Outputs if their normal application functions of temperature and voltage monitoring are not needed. Their configuration is controlled in the GPIOctrl register. The NTC/IO0 pin may be configured as a push-pull output, an open-drain driver with internal pull-up, or as a three-stated pin. When configured as a push-pull or open drain output, the output high voltage is equal to the internally regulated supply voltage, which is nominally at 3.3V. When the output function is disabled, an external circuit may drive the pin as an input with a voltage range of 0-3.3V. The input function may be used whether or not the pin is driven by the ISL6295. In addition, the input function may be disabled, in which case, the input buffer is "SAMPDIV" SAMPLE INTERVAL Value = 0 0.5s Value = 1 1.0s Value = 2 2.0s Value = 3 4.0s Value = 4 8.0s Value = 5 16.0s Value = 6 32.0s Value = 7 64.0s ISL6295 |
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