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LM12454 Datasheet(PDF) 25 Page - Texas Instruments |
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LM12454 Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 45 page  LM12454, LM12458, LM12H458 www.ti.com SNAS079A – MAY 2004 – REVISED FEBRUARY 2006 Pin Descriptions (continued) Synchronization input/output. When used as an output, it is designed to drive capacitive loads of 100 pF or less. External buffers are necessary for driving higher load capacitances. SYNC is an input if the Configuration register's “I/O Select” bit is low. A rising edge on this pin causes the internal S/H to hold the input signal. The next rising clock edge either starts a SYNC conversion or makes a comparison to a programmable limit depending on which function is requested by a programming instruction. This pin will be an output if “I/O Select” is set high. The SYNC output goes high when a conversion or a comparison is started and low when completed. (See Section 2.2). An internal reset after power is first applied to the LM12(H)454/8 automatically sets this pin as an input. Bus Width input pin. This input allows the LM12(H)454/8 to interface directly with either an 8- BW or 16-bit data bus. A logic high sets the width to 8 bits and places D8–D15 in a high impedance state. A logic low sets the width to 16 bits. Active low interrupt output. This output is designed to drive capacitive loads of 100 pF or less. External buffers are necessary for driving higher load capacitances. An interrupt signal INT is generated any time a non-masked interrupt condition takes place. There are eight different conditions that can cause an interrupt. Any interrupt is reset by reading the Interrupt Status register. (See Section 2.3.) Active high Direct Memory Access Request output. This output is designed to drive capacitive loads of 100 pF or less. External buffers are necessary for driving higher load DMARQ capacitances. It goes high whenever the number of conversion results in the conversion FIFO equals a programmable value stored in the Interrupt Enable register. It returns to a logic low when the FIFO is empty. LM12(H)454/8 ground connection. It should be connected to a low resistance and inductance GND analog ground return that connects directly to the system power supply ground. The eight (LM12(H)458) or four (LM12454) analog inputs. A given channel is selected through the instruction RAM. Any of the channels can be configured as an independent IN0–IN7 (IN0–IN3 LM12H454 LM12454) single-ended input. Any pair of channels, whether adjacent or non-adjacent, can operate as a fully differential pair. S/H IN+ S/H IN- The LM12454's non-inverting and inverting inputs to the internal S/H. MUXOUT+ MUXOUT- The LM12454's non-inverting and inverting outputs from the internal multiplexer. The negative reference input. The LM12(H)454/8 operate with 0V = VREF-= VREF+. This pin VREF- should be bypassed to ground with a parallel combination of 10 µF and 0.1 µF (ceramic) capacitors. The positive reference input. The LM12(H)454/8 operate with 0V = VREF+ = VA+. This pin VREF+ should be bypassed to ground with a parallel combination of 10 µF and 0.1 µF (ceramic) capacitors. The internal 2.5V bandgap's output pin. This pin should be bypassed to ground with a 100 VREFOUT µF capacitor. 1.0 Functional Description The LM12454 and LM12(H)458 are multi-functional Data Acquisition Systems that include a fully differential 12- bit-plus-sign self-calibrating analog-to-digital converter (ADC) with a two's-complement output format, an 8- channel (LM12(H)458) or a 4-channel (LM12454) analog multiplexer, an internal 2.5V reference, a first-in-first-out (FIFO) register that can store 32 conversion results, and an Instruction RAM that can store as many as eight instructions to be sequentially executed. The LM12454 also has a differential multiplexer output and a differential S/H input. All of this circuitry operates on only a single +5V power supply. The LM12(H)454/8 have three modes of operation: 12-bit + sign with correction 8-bit + sign without correction 8-bit + sign comparison mode (“watchdog” mode) The fully differential 12-bit-plus-sign ADC uses a charge redistribution topology that includes calibration capabilities. Charge re-distribution ADCs use a capacitor ladder in place of a resistor ladder to form an internal DAC. The DAC is used by a successive approximation register to generate intermediate voltages between the voltages applied to VREF− and VREF+. These intermediate voltages are compared against the sampled analog input voltage as each bit is generated. The number of intermediate voltages and comparisons equals the ADC's resolution. The correction of each bit's accuracy is accomplished by calibrating the capacitor ladder used in the ADC. Copyright © 2004–2006, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: LM12454 LM12458 LM12H458 |
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