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LM12454 Datasheet(PDF) 28 Page - Texas Instruments

Part # LM12454
Description  LM12454/LM12458/LM12H458 12-Bit Sign Data Acquisition System with Self-Calibration
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LM12454 Datasheet(HTML) 28 Page - Texas Instruments

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LM12454, LM12458, LM12H458
SNAS079A – MAY 2004 – REVISED FEBRUARY 2006
www.ti.com
When the LM12(H)454/8 are used in the “watchdog” mode with external synchronization, two rising edges on the
SYNC input are required to initiate two comparisons. The first rising edge initiates the comparison of the selected
analog input signal with Limit #1 (found in Instruction RAM “01”) and the second rising edge initiates the
comparison of the same analog input signal with Limit #2 (found in Instruction RAM “10”).
Bit 9 is the TIMER bit. When Bit 9 is set to “1”, the Sequencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no “watchdog” comparisons or analog-to-digital conversions will be performed.
Bit 10 selects the ADC conversion resolution. Setting Bit 10 to “1” selects 8-bit + sign and when reset to “0”
selects 12-bit + sign.
Bit 11 is the “watchdog” comparison mode enable bit. When operating in the “watchdog” comparison mode, the
selected analog input signal is compared with the programmable values stored in Limit #1 and Limit #2 (see
Instruction RAM “01” and Instruction RAM “10”). Setting Bit 11 to “1” causes two comparisons of the selected
analog input signal with the two stored limits. When Bit 11 is reset to “0”, an 8-bit + sign or 12-bit + sign
(depending on the state of Bit 10 of Instruction RAM “00”) conversion of the input signal can take place.
Table 4. LM12(H)454/8 Memory Map for 16-Bit Wide Data Bus (BW = “0”, Test Bit = “0” and A0 = Don't
Care)
A4
A3
A2
A1
Pur
Typ
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
pos
e
e
0
0
0
Instr
uctio
0
to
n
RA
Wat
M
Tim
Syn
VIN− (MUXOUT−) VIN+ (MUXOUT+) Pau
Loo
R/W
Acquisition Time
ch-
8/12
(RA
er
c
(1)
(1)
se
p
dog
1
1
1
M
Poin
ter =
00)
0
0
0
Instr
uctio
0
to
n
1
1
1
RA
M
R/W
Don't Care
>/<
Sign
Limit #1
(RA
M
Poin
ter =
01)
0
0
0
Instr
uctio
0
to
n
1
1
1
RA
M
R/W
Don't Care
>/<
Sign
Limit #2
(RA
M
Poin
ter =
10)
Conf
igur
Cha
DIA
Auto
Stan
Auto
atio
Test
RAM
i/O
r
Full
Res
1
0
0
0
R/W
Don't Care
G *
Zero
d-
-
Start
n
= 0
Pointer
Sel
Mas
CAL
et
(2)
ec
by
Zero
Regi
k
ster
Inter
rupt
Number of Conversions in
Sequencer
Ena
INT
INT
INT
INT
INT
INT
INT
INT
1
0
0
1
R/W
Conversion FIFO to Generate
Address to
ble
7
6
5
4
3
2
1
0
INT2
Generate INT1
Regi
ster
(1)
LM12454 (Refer to Table 7).
(2)
LM12(H)458 only. Must be set to “0” for the LM12454.
28
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Copyright © 2004–2006, Texas Instruments Incorporated
Product Folder Links: LM12454 LM12458 LM12H458


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