LM12454, LM12458, LM12H458
SNAS079A – MAY 2004 – REVISED FEBRUARY 2006
3.0 Other Registers and Functions
3.1 INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4–A1, BW = 0) or 1010x (A4–A0, BW = 1). The
corresponding flag in the Interrupt Status register goes high (“1”) any time that an interrupt condition takes place,
whether an interrupt is enabled or disabled in the Interrupt Enable register. Any of the active (“1”) Interrupt Status
register flags are reset to “0” whenever this register is read or a device reset is issued (see Bit 1 in the
Bit 0 is set to “1” when a “watchdog” comparison limit interrupt has taken place.
Bit 1 is set to “1” when the Sequencer has reached the address stored in Bits 8–10 of the Interrupt Enable
Bit 2 is set to “1” when the Conversion FIFO's limit, stored in Bits 11–15 of the Interrupt Enable register, has
Bit 3 is set to “1” when the single-sample auto-zero has been completed.
Bit 4 is set to “1” when an auto-zero and full linearity self-calibration has been completed.
Bit 5 is set to “1” when a Pause interrupt has been generated.
Bit 6 is set to “1” when a low-supply voltage condition (VA+ < 4V) has taken place.
Bit 7 is set to “1” when the LM12(H)454/8 return from power-down to active mode.
Bits 8–10 hold the Sequencer's actual instruction address while it is running.
Bits 11–15 hold the actual number of conversions stored in the Conversion FIFO while the Sequencer is running.
3.2 LIMIT STATUS REGISTER
The read-only register is located at address 1101 (A4–A1, BW = 0) or 1101x (A4–A0, BW = 1). This register is
used in tandem with the Limit #1 and Limit #2 registers in the Instruction RAM. Whenever a given instruction's
input voltage exceeds the limit set in its corresponding Limit register (#1 or #2), a bit, corresponding to the
instruction number, is set in the Limit Status register. Any of the active (“1”) Limit Status flags are reset to “0”
whenever this register is read or a device reset is issued (see Bit 1 in the Configuration register). This register
holds the status of limits #1 and #2 for each of the eight instructions.
Bits 0–7 show the Limit #1 status. Each bit will be set high (“1”) when the corresponding instruction's input
voltage exceeds the threshold stored in the instruction's Limit #1 register. When, for example, instruction 3 is a
“watchdog” operation (Bit 11 is set high) and the input for instruction 3 meets the magnitude and/or polarity data
stored in instruction 3's Limit #1 register, Bit 3 in the Limit Status register will be set to a “1”.
Bits 8–15 show the Limit #2 status. Each bit will be set high (“1”) when the corresponding instruction's input
voltage exceeds the threshold stored in the instruction's Limit #2 register. When, for example, the input to
instruction 6 meets the value stored in instruction 6's Limit #2 register, Bit 14 in the Limit Status register will be
set to a “1”.
The LM12(H)454/8 have an on-board 16-bit timer that includes a 5-bit pre-scaler. It uses the clock signal applied
to pin 23 as its input. It can generate time intervals of 0 through 221 clock cycles in steps of 25. This time interval
can be used to delay the execution of instructions. It can also be used to slow the conversion rate when
converting slowly changing signals. This can reduce the amount of redundant data stored in the FIFO and
retrieved by the controller.
The user-defined timing value used by the Timer is stored in the 16-bit READ/WRITE Timer register at location
1011 (A4–A1, BW = 0) or 1011x (A4–A0, BW = 1) and is pre-loaded automatically. Bits 0–7 hold the preset
value's low byte and Bits 8–15 hold the high byte. The Timer is activated by the Sequencer only if the current
instruction's Bit 9 is set (“1”). If the equivalent decimal value “N” (0
≤ N ≤ 216 − 1) is written inside the 16-bit Timer
register and the Timer is enabled by setting an instruction's bit 9 to a “1”, the Sequencer will delay the same
instruction's execution by halting at state 3 (S3), as shown in Figure 14, for 32 × N + 2 clock cycles.
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