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LM12454 Datasheet(PDF) 35 Page - Texas Instruments

Part # LM12454
Description  LM12454/LM12458/LM12H458 12-Bit Sign Data Acquisition System with Self-Calibration
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Manufacturer  TI1 [Texas Instruments]
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LM12454 Datasheet(HTML) 35 Page - Texas Instruments

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LM12454, LM12458, LM12H458
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SNAS079A – MAY 2004 – REVISED FEBRUARY 2006
3.4 DMA
The DMA works in tandem with Interrupt 2. An active DMA Request on pin 32 (DMARQ) requires that the FIFO
interrupt be enabled. The voltage on the DMARQ pin goes high when the number of conversions in the FIFO
equals the 5-bit value stored in the Interrupt Enable register (bits 11–15). The voltage on the INT pin goes low at
the same time as the voltage on the DMARQ pin goes high. The voltage on the DMARQ pin goes low when the
FIFO is emptied. The Interrupt Status register must be read to clear the FIFO interrupt flag in order to enable the
next DMA request.
DMA operation is optimized through the use of the 16-bit data bus connection (a logic “0” applied to the BW pin).
Using this bus width allows DMA controllers that have single address Read/Write capability to easily unload the
FIFO. Using DMA on an 8-bit data bus is more difficult. Two read operations (low byte, high byte) are needed to
retrieve each conversion result from the FIFO. Therefore, the DMA controller must be able to repeatedly access
two constant addresses when transferring data from the LM12(H)454/8 to the host system.
4.0 FIFO
The result of each conversion stored in an internal read-only FIFO (First-In, First-Out) register. It is located at
1100 (A4–A1, BW = 0) or 1100x (A4–A0, BW = 1). This register has 32 16-bit wide locations. Each location holds
13-bit data. Bits 0–3 hold the four LSB's in the 12 bits + sign mode or “1110” in the 8 bits + sign mode. Bits 4–11
hold the eight MSB's and Bit 12 holds the sign bit. Bits 13–15 can hold either the sign bit, extending the register's
two's complement data format to a full sixteen bits or the instruction address that generated the conversion and
the resulting data. These modes are selected according to the logic state of the Configuration register's Bit 5.
The FIFO status should be read in the Interrupt Status register (Bits 11–15) to determine the number of
conversion results that are held in the FIFO before retrieving them. This will help prevent conversion data
corruption that may take place if the number of reads are greater than the number of conversion results
contained in the FIFO. Trying to read the FIFO when it is empty may corrupt new data being written into the
FIFO. Writing more than 32 conversion data into the FIFO by the ADC results in loss of the first conversion data.
Therefore, to prevent data loss, it is recommended that the LM12(H)454/8's interrupt capability be used to inform
the system controller that the FIFO is full.
The lower portion (A0 = 0) of the data word (Bits 0–7) should be read first followed by a read of the upper portion
(A0 = 1) when using the 8-bit bus width (BW = 1). Reading the upper portion first causes the data to shift down,
which results in loss of the lower byte.
Bits 0–12 hold 12-bit + sign conversion data. Bits 0–3 will be 1110 (LSB) when using 8-bit plus sign resolution.
Bits 13–15 hold either the instruction responsible for the associated conversion data or the sign bit. Either mode
is selected with Bit 5 in the Configuration register.
Using the FIFO's full depth is achieved as follows. Set the value of the Interrupt Enable register's Bits 11–15 to
11111 and the Interrupt Enable register's Bit 2 to a “1”. This generates an external interrupt when the 31st
conversion is stored in the FIFO. This gives the host processor a chance to send a “0” to the LM12(H)454/8's
Start bit (Configuration register) and halt the ADC before it completes the 32nd conversion. The Sequencer halts
after the current (32) conversion is completed. The conversion data is then transferred to the FIFO and occupies
the 32nd location. FIFO overflow is avoided if the Sequencer is halted before the start of the 32nd conversion by
placing a “0” in the Start bit (Configuration register). It is important to remember that the Sequencer continues to
operate even if a FIFO interrupt (INT 2) is internally or externally generated. The only mechanisms that stop
the Sequencer are an instruction with the PAUSE bit set to “1” (halts before instruction execution), placing a “0”
in the Configuration register's START bit, or placing a “1” in the Configuration register's RESET bit.
5.0 Sequencer
The Sequencer uses a 3-bit counter (Instruction Pointer, or IP, in Figure 9) to retrieve the programmable
conversion instructions stored in the Instruction RAM. The 3-bit counter is reset to 000 during chip reset or if the
current executed instruction has its Loop bit (Bit 1 in any Instruction RAM “00”) set high (“1”). It increments at the
end of the currently executed instruction and points to the next instruction. It will continue to increment up to 111
unless an instruction's Loop bit is set. If this bit is set, the counter resets to “000” and execution begins again with
the first instruction. If all instructions have their Loop bit reset to “0”, the Sequencer will execute all eight
instructions continuously. Therefore, it is important to realize that if less than eight instructions are programmed,
the Loop bit on the last instruction must be set. Leaving this bit reset to “0” allows the Sequencer to execute
“unprogrammed” instructions, the results of which may be unpredictable.
Copyright © 2004–2006, Texas Instruments Incorporated
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